fpga bashir2000 0 547
Hello dear all, I have run into a problem regarding the FPGA. The FPGA output signal amplitude is 3.3, and to drive my switches, I need to increase t...

Spartan IOB Input Switching Characteristic Michael 2 179
Hi, I have a fully routed Spartan3(Alliance 9,2) that I would like to keep the routing and only change the "IOB Input Switching Characteristic" f...

MAX II CPLD and I2S Clock divider jitter Mark 0 283
I have MAX II CPLD with clock of 24.576 MHz as input coming from the external crystal oscillator. This clock is used inside the CPLD to generate sub...

fpga express 3.6 electrocoder 6 266
i want "fpga express 3.6" setup program. i have "ftp://ftp.xilinx.com/ pub/swhelp/M3.1i_updates/fpgaexp35.exe" update files. i want setup program. t...

How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board Pratap 11 197
Hi, I want to delay a signal precisely by taking out the signal from the FPGA so that it can be fed to another chip which can control the delay thr...

Measuring the delay between two rising edges in modelsim simulation through command/tcl script and writing them to a file. Pratap 4 200
Hi, I want to measure the delay between two rising edges in modelsim simulation. There are commands in spice like tools where the .measure statemen...

Problems connecting with Xilinx Spartan-6 FPGA DaMunky89 2 423
Currently, when trying to download the bitstream to this SP605 board, I get the following error: FPGA configuration encountered errors. Program F...

Xilinx EDK - max array size Tobias 2 253
Hi I want to handle an array with some hundred elements. Here is an example code: #include "xmk.h" #include "sys/init.h" #include "platform...

Via in Hyperlynx linesim Mark 2 235
Is there anyway to specify via in HyperLynx LineSim? For example, I have a transmission line with microstrip of length 20mm on top layer , then goes...

SRL as a synchroniser Allan 6 194
Hi, At a client's site I have some legacy VHDL code that is being synthesised with Xilinx XST 13.1 with Virtex 6 as a target. This code has so...