clock net placement and routing

I am using ISE 12.2 and targeting virtex6 LX760. When I take the netlist through map I get the following error: ERROR:Place:1153 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock IOB component <SWCLKTCK> is placed at site <IOB_X0Y179>. The corresponding BUFGCTRL component <SWCLKTCK_ibuf> is placed at site <BUFGCTRL_X0Y2>. The clock IO can use the fast path between the IOB and the Clock Buffer if a) the IOB is placed on a Global Clock Capable IOB site that has the fastest

XC4028's to offer

Hi to all, Excuse me if this is an inappropriate spot for such a request but there aren't many places on the Net where I can post an offer on Xilinx components. I am presently making some room in my inventory and I came across 5 pieces of XILINX XC4028XLA BG352AKP9913 (D1078919A). Guaranteed to be fully operational, they've been programmed once and tested only for a prototype. I will accept any decent offer. I can also send one for evaluation. If anyone is interested, please drop me an email at your convenience. Thank you. Mark L. -----------------

MPMC without MCB on Spartan-6

Hi, Is there a way to hack the MPMC into not using the MCB (but the softcore MIG) on Spartan-6? The MPMC datasheet says no, but since the MIG source code is mostly behavioral (iirc), maybe there is a way around this. I have a board with DDR SDRAM and a pinout that is not compatible with the MCB, and my custom softcore platform (that is not using the MCB) randomly crashes when running complex software (Linux systems etc.). I'm suspecting a DRAM problem. It is stable on Virtex-4, tested on the ML401 board. I would like to test my custom board with Microblaze in order to put potenti

Spartan6 distributed RAM- why no x4 and x8 configurations ?

Hi to all, I have installed Webpack 12.2 and am getting acquainted with Spartan6. While reading "Spartan6 CLB User Guide( ug384.pdf )" I came up to page 15 -"Distributed RAM and MEmory (SLICEM only)" and noticed that there is no x4 or x8 configuration, and there is no explanation of that, neither it is self-evident from diagrams. Is there some fundamental routing resources limitation or something similar ?

debit source code

Hey, I was going through debit to experiment with bitstream formats. Apparently the site (www.ulogic.org) seems to be down and I couldn't get the source code by that time. Does anyone have the source code?

Tutorial on timing constraints

Xilinx Guru Austin Lesea penned a great tutorial on timing constraints in the latest issue of Xcell Journal. Here is a link to the flash version http://cde.cerosmedia.com/1G4c56e6f64dfe8012.cde/page/46. You can also download the pdf of the entire issue at http://www.xilinx.com/publications/archives/xcell/Xcell72.pdf. Austin's piece is on page 46.

dct verilog

hi, I downloaded the DCT verilog module from the altera website. http://www.altera.com/support/examples/verilog/ver_dct.html I ran a simulation using simple testbench that sends 0,1,2,...63 as the input parameters. The dct_out(output signal) never sends out any result and it always xxxxxx. From the initial basic understanding of the code, the reading the writing of local memory seems done incorrectly. Also the original code has some compilation errors which is given below. Some of the reg needed to be converted to wires to compile. It didn't not seem to alter the functionality.

BRAM initialization in EDK 12.2

Hi! Xilinx changed BRAM initialization process in EDK 12.2. There is no system_conf configuration. Now EDK use mem-files to init BRAMs. In my project they are filled with data, but in Modelsim or Isim my software do not executes by CPU(PPC). What is wrong? --------------------------------------- Posted through http://www.FPGARelated.com

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Plotting sampled data in Matlab

I'm simulating some filter hardware in Modelsim, and need a way to display the output with a virtual anti-alias filter. Is there a Matlab facility for this? plot doesn't seem to have any good option for this. I tried interp1, and it's better than nothing, but the highest order interpolator seems to be 4-tap ('spline'). I could do a higher order filter myself, but feel that Matlab probably has the ideal functionality already, if I only knew how to invoke it. Any thoughts. Example: Generate a DC to Nyquist sweep >> t = 0:0.001:1; >> y = chirp(t, 0, 1, 500); >> plot(y) Look

Spartan-6 - What is the IODRP2_MCB??

Hi, While studying the MIG ref design for Spartan-6 I was surprised to find a IODRP2_MCB which doesn't have any documentation. Any information about it? Thanks

New Application Note: Multiple configurations for Altera FPGAs

Hi, After seeing a number of customers struggling with this issue, I have written a detailed ApNote showing how to implement a multiple configuration system for Altera FPGAs. The example is a Cyclone III using Active Serial mode / EPCS (on a DE0 board), but it is easily translatable to any other Altera FPGA/board. It is not complex, but getting everything right from the documentation is not absolutely obvious. The ApNote and the design files are available at the top of the list at: http://www.alse-fr.com/apnotes.php Anyone spotting a discrepancy, please let me know. Hope

Mismatch between Xilinx FIR interpolation filter

Hi everyone, I'm currently using a design with a 5 /4 interpolation Filter used to convert a signal sampled @ 80 MHz to 100 MHz. The Interpolation filter is designed using FIR compiler 3.2 (ISE 10) and implemented on a Virtex 5 FPGA. The problem is present in simulation too. For this purpose we have used a 33-tap filter. The filter works well however there is an implementation difference between Matlab and the Xilinx core. I used a step response to characterize both systems and I obtain slightly different results. There is a slight phase delay between the Matlab implementation (wi

Text compression Huffman Encoder and Decoder

Hi all, I am working on text Huffman Encoder and Decoder to be implemented on FPGA. and here are things which are not clear for me. 1.Will the binary tree be constructed by software and then the coded data be taken and VHDL coded OR can I construct the Binary tree using VHDL? and I need some hint. kude --------------------------------------- Posted through http://www.FPGARelated.com

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Xilinx Xcell Journal Issue 72 Now available

Hi folks, my team here at Xilinx just published a new issue of Xcell Journal: http://www.xilinx.com/publications/xcellonline/index.htm. This issue has some great tutorial and how-to articles. Check out Austin Lesea's tutorial on timing constraints on page 46. The issue also includes features on the new 7 Series and Virtex-5QV rad-hard FPGA. Also, if you would like to contribute to Xcell, just shoot me an email at xcell(at)xilinx.com Cheers, Mike Santarini

Altera blasters missing ESD protection

Ive seen some different blasters now and they are all missing ESD protection on the jtag pins. A colleague has blown quite a few now. The jtag signals only have a small L and then goes direct into level translators that has ESD warning in their datasheets. Does anyone know of a protected or opto isolated device within a reasonable price?

FPGA PCI BOARD .. Few Questions

I am designing myself a FPGA board to interact with a PCI Bus and i have couple questions. First, Is it mandatory to have 2 power layers (GND + VCC)? Second, i just got a quote from a PCB manufactury and it should cost me $250 to make a board. Is it possible to find a cheaper board? The cheapest i found was Dragon Board from Knjn with a price of $300. Once i heared about a Insight Eletronics Board but i could not find it ... Any sugestions? Thats all for now!! Thank you! --------------------------------------- Posted through http://www.FPGARelated.com

Getting started with FPGA

Hi, I'm interested in learning more about FPGAs in a hands on way. Can anyone recommend an inexpensive set of tools to get started with? My wishlist is: I'd like to develop on Linux, I'd like to spend no more than a few hundred $ on a starter kit, I'd like to learn using the tools and up-to-date skills that are relevant to the more high end set ups available. Which is better to start with, Xilinx or Altera or something else? Is there a choice between Verilog and VHDL to be made, or can both be tried out just as easily? At the moment I am not too bothered about specific application

I have problem in writing testbench

This is my testbench code. When I load it and want see signals in wave, after I add it, wave is empty. I do everything but the problem isn't solve. Can anyone help me? library ieee; use ieee.std_logic_1164.all; use work.all; entity test_dff is end test_dff; architecture behavioral of test_dff is component dff port(din,clk,rst:in std_logic; dout:out std_logic); end component; signal clk1:std_logic:='0'; signal rst1:std_logic:='0'; signal din1:std_logic; signal dout1:std_logic; begin unit0: dff port map(din=>din1,clk=>clk1,rst

CoreTimer programming in Actel SoftConsole

Hello, I am trying to measure the execution time of some code using a CoreTimer block connected to a Cortex-M1 processor design in an Actel Fusion part. My problem is that TMR_current_value() always returns 0. I am trying to run in TMR_ONE_SHOT_MODE but I have also tried continuous mode but no change. I have also double checked that the CoreTimer block is attached to the APB bus and that the base address in hardware corresponds to CORETMR_BASE_ADDR in my C source. Can anyone suggest a reason that TMR_current_value() always returns 0? Below I attache my C code. int

XC5VTX240T-2FF1759I4177

Could someone please help me to identify the suffix, "4177", on this Virtex-5 device and what it calls out as well as the meaning? Could I use this device in replace of the XC5VTX240T-2FF1759I (Without 4177 suffix)? Avnet advertizes them both however the one with the "4177" suffix is roughly $1,000.00 more? It seems it wouldnt be a custom device or customer code as they advertize both to the public? Anyones Help on this is appreciated. XC5VTX240T-2FF1759I4177 ? Thank you, Dave

Spartan3a: improving DCM performance and "To achieve optimal frequency synthesis performance..." warning

Hi guys, Can anyone explain the following INFO alert I saw in my ISE build log? INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp clock_generator/DCM_SP_INST, consult the device Interactive Data Sheet. This is on a Spartan3a design which uses a DCM to multiply the incoming 25MHz clock up to 50MHz, then feeds it to another DCM which generates CLK0 and CLK90 (0 and 90 degree phase-shifted clocks) from the 50MHz clock. The 0deg clock is used to drive the CPU, SDRAM controller and other stuff

Multiple builds with different top-level generic

Hi, I'm working on a Xilinx FPGA design (VHDL) that uses a top level generic, and need to build multiple versions of the FPGA where the generic is the only thing that changes. The generic is used to select different modules to be used in the FPGA, the modules can't all fit in the FPGA together. Currently there are 4 different settings for the generic, and for a release I need to build the FPGA with each of the different generic options. What I am looking for is advice on how to set up a script/makefile to generate the builds in parallel, whilst ensuring that the results a

VHDL newbie- stuck just weeks before project submission :(..please help

Hello, For my Masters project, I'm trying to implement a multiplier, and a MAC where the outputs are calculated per clock cycle and stored in a text file which can then be used for further processing. However, both these designs are giving out partial products(I guess they are partial products) at the output too, before they give the final result..I've tried changing the codes, changing clock frequency in testbench etc. but nothing seems to work... Is there any way to implement a output_ready signal for multipliers/ adders?(I saw a few codes using shifter for rdy, but could not