LCD test on Spartan 3E FPGA 5 5 (11/27/2013 3:44:13 PM)
Hi, I got a problem that I cannot understand how to display on the LCD of Sp= artan 3E FPGA. Then, how to get the inputs and outputs of a 16-bit Ripple C= arry Adder to show on LCD? Please any one who ha...
ttungl (5)

FPGA Cryptosystem 9 4 (11/21/2013 11:04:10 PM)
Hello all Proposed idea from my research to date: Two FPGA encryption modules: Both will have an identical encryption algorit= hm; key management something I need to research further. Bob has plain text m...
cyounge28 (2)

Call for Papers: IAENG International Conference on Software Engineering ICSE 2014 0 4 (11/26/2013 7:19:04 AM)
Call for Papers: IAENG International Conference on Software Engineering ICS= E 2014 Draft Manuscript submission deadline: 8 December, 2013 =20 Camera-Ready papers & registration deadline: 10 January, 2014...
iaeng_imecs_wce_wcecs_c (84)

Interface Xilinx KC705 to BeagleBone? 14 96 (7/22/2012 8:27:45 PM)
I'm playing with the idea of interfacing a BeagleBone (cheap dual ARM Cortex A8 board) to a Xilinx KC705 Kintex development board. This will give me much more CPU processing power than a microblaze could. ...
pete_fraser (24)

microZed adventures 23 8 (11/22/2013 4:57:12 PM)
We're into this signal processing project, using a microZed/ZYNQ thing as the compute engine. After a week or so of work by an FPGA guy and a programmer, we can now actually read and write an FPGA regi...
jjlarkin (641)

Mill: FPGA version? 6 6 (11/22/2013 3:20:09 PM)
I've been wondering if there could be a successful (not too large, reasonable clock frequency) soft-core FPGA version of a low end variant of the Mill. One issue with FPGAs is that only two-port memory is av...
jhallen (47)