fpgabashir2000 0 547 Hello dear all, I have run into a problem regarding the FPGA. The FPGA output signal amplitude is 3.3, and to drive my switches, I need to increase t...
Spartan IOB Input Switching CharacteristicMichael 2 179 Hi,
I have a fully routed Spartan3(Alliance 9,2) that I would like to keep
the routing and only change the "IOB Input Switching Characteristic" f...
MAX II CPLD and I2S Clock divider jitterMark 0 283 I have MAX II CPLD with clock of 24.576 MHz as input coming from the
external crystal oscillator. This clock is used inside the CPLD to
generate sub...
fpga express 3.6electrocoder 6 266 i want "fpga express 3.6" setup program. i have "ftp://ftp.xilinx.com/
pub/swhelp/M3.1i_updates/fpgaexp35.exe" update files. i want setup
program. t...
Problems connecting with Xilinx Spartan-6 FPGADaMunky89 2 423 Currently, when trying to download the bitstream to this SP605 board,
I get the following error:
FPGA configuration encountered errors.
Program F...
Xilinx EDK - max array sizeTobias 2 253 Hi
I want to handle an array with some hundred elements.
Here is an example code:
#include "xmk.h"
#include "sys/init.h"
#include "platform...
Via in Hyperlynx linesimMark 2 235 Is there anyway to specify via in HyperLynx LineSim? For example, I
have a transmission line with microstrip of length 20mm on top layer ,
then goes...
SRL as a synchroniserAllan 6 194 Hi,
At a client's site I have some legacy VHDL code that is being synthesised
with Xilinx XST 13.1 with Virtex 6 as a target.
This code has so...