Hi all:

I'm pleased to announce the release of MyHDL 0.5.

MyHDL is an open-source package for using Python as a hardware
description and verification language. Moreover, it can convert
a design to Verilog. Thus, MyHDL provides a complete path
from Python to an FPGA implementation.

MyHDL 0.5 has many new features, in particular with regard to
conversion to Verilog. The converter automates certain tasks
that are hard in Verilog directly. The Verilog output code
works well with popular FPGA synthesis tools.

For a complete overview, go here:
   http://myhdl.jandecaluwe.com/doku.php/overview

The manual is here:
   http://www.jandecaluwe.com/Tools/MyHDL/manual/MyHDL.html

To find out the details of what's new, go here:
   http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5

You can download the release from SourceForge:
   http://sourceforge.net/project/showfiles.php?group_id=91207

Best regards,

Jan Decaluwe

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Jan Decaluwe wrote:

> Hi all:
> 
> I'm pleased to announce the release of MyHDL 0.5.
> 
> MyHDL is an open-source package for using Python as a hardware
> description and verification language. Moreover, it can convert
> a design to Verilog. Thus, MyHDL provides a complete path
> from Python to an FPGA implementation.
> 
> MyHDL 0.5 has many new features, in particular with regard to
> conversion to Verilog. The converter automates certain tasks
> that are hard in Verilog directly. The Verilog output code
> works well with popular FPGA synthesis tools.
> 
> For a complete overview, go here:
>   http://myhdl.jandecaluwe.com/doku.php/overview
> 
> The manual is here:
>   http://www.jandecaluwe.com/Tools/MyHDL/manual/MyHDL.html
> 
> To find out the details of what's new, go here:
>   http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5
> 
> You can download the release from SourceForge:
>   http://sourceforge.net/project/showfiles.php?group_id=91207
> 
> Best regards,
> 
> Jan Decaluwe

Looks impressive, and interesting.

  Do you have any Simulation benchmark indications, and any
simple, example 'complete' side-by-side projects ?
  By simple, I mean things like  16/24/32 bit Up/Dn/ReLoad counter,
perhaps a DDS as well, and since it seems to have good ROM/RAM support, 
a 7 segment display counter ?

-jg

Jim Granville wrote:

>  Do you have any Simulation benchmark indications,

Simulation performance is basically limited by the Python
interpreter. Compared to mainstream HDL simulators, I
expect a performance degradation similar to Python versus C.
Therefore, raw simulation performance is not a good argument
in favor of MyHDL at this point. Fortunately, there are
many other good reasons :-)

 > and any
> simple, example 'complete' side-by-side projects ?
>  By simple, I mean things like  16/24/32 bit Up/Dn/ReLoad counter,
> perhaps a DDS as well, and since it seems to have good ROM/RAM support, 
> a 7 segment display counter ?

No, but it seems like a good idea to set up such a page on
the web site. Perhaps you have a pointer to Verilog/VHDL
code for such relevant designs?

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Jan Decaluwe wrote:

> Jim Granville wrote:
> 
>>  Do you have any Simulation benchmark indications,
> 
> 
> Simulation performance is basically limited by the Python
> interpreter. Compared to mainstream HDL simulators, I
> expect a performance degradation similar to Python versus C.
> Therefore, raw simulation performance is not a good argument
> in favor of MyHDL at this point. Fortunately, there are
> many other good reasons :-)

You might be surprised, which was why I was curious.
There are functional simulation, and timing simulation tasks,
- you might not be as slow as you think, on the functional areas,
where higher levels can help.

> 
>  > and any
> 
>> simple, example 'complete' side-by-side projects ?
>>  By simple, I mean things like  16/24/32 bit Up/Dn/ReLoad counter,
>> perhaps a DDS as well, and since it seems to have good ROM/RAM 
>> support, a 7 segment display counter ?
> 
> 
> No, but it seems like a good idea to set up such a page on
> the web site. Perhaps you have a pointer to Verilog/VHDL
> code for such relevant designs?

I'll see what I can find, and email some to you.
Such simple examples are not as common as they should be,
on vendors web sites.

-jg

Jim Granville wrote:

> I'll see what I can find, and email some to you.
> Such simple examples are not as common as they should be,
> on vendors web sites.

For those interested, I have started a "MyHDL Cookbook",
with a first example:

   http://myhdl.jandecaluwe.com/doku.php/cookbook:jc2

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com