Xilinx Methodology Questions : Unconstrained Paths and DLL output phase alignment. 1 158 (7/2/2003 2:24:33 PM)
Hi I have two questions regarding Xilinx designs. [1] How do I identify which paths the static timing analyzer considers to be unconstrained? This has been an ongoing, frustrating task for me. I am an extre...
John

VHDL variable setup and propogations 1 57 (7/2/2003 4:35:22 AM)
Greetings, I am having a strage time with some code I recently wrote to implement a UART - the code is working fine now, but a problem cropped up that is baffling me. This design is being synthesized in Xil...
Matt

Need help in capturing serial data using FPGA and ethernet interface 0 177 (7/2/2003 6:52:26 AM)
hello, i want to capture 2 mbps serial data stream through my ethernet card. i already have a Virtex FPGA based hardware and I want to add it this data logging funtionality. I want to use FPGA to convert the r...
e_engineer00 (6)

Celoxica feedback 0 130 (7/1/2003 9:08:49 PM)
Can anyone provide feedback on Celoxica. Do they meet all of the claims? Performance obtained ? Pros and cons? ...
Alain

NAND flash file 1 139 (7/1/2003 3:41:25 PM)
Does anyone know where I can find the xapp354_verilog or xapp354_VHDL files for NAND flash? I went to the Xilinx ftp site, and they were not listed there. Thanks.--Matt ...
mduane

Seriell Decoder possibly in ABEL for Lattice CPLD 1 131 (7/1/2003 2:45:20 PM)
Hi there I'm not very familar with HDL, but I have to realize a small project with Lattice CPLD. Up to now the most things are working fine, but now I need help: I'm searching for a device to implement (possib...
tispace

device selection for game system 0 110 (7/1/2003 3:47:59 PM)
I'm working on implementing a custom game boy advance cartrige with the following features: - 4-16MByte flash rom (bank switched to a 24 pin buss) - 32kbyte save ram (game state save, can be stored in flash ...
david

Celoxica DK1 to Xilinx Spartan II 1 116 (7/1/2003 10:38:07 AM)
Hello, I have written a program to run on the Celoxica RC100 board and compiled it to edif file. When i use the Xilinx Design Manager to convert it to a bit file, it always fail during the mapping stage say...
Triax

Eighty layers of metal! 36 99 (6/25/2003 3:24:54 PM)
Article intended for FPGA-types has a nice summary (for dummies like me) of the state of the wire-delay/interconnect problem: http://www.us.design-reuse.com/articles/article5786.html "James Meindl at the Geor...
Robert

I need a commercial PCI FPGA board, please help 5 133 (6/26/2003 8:49:26 PM)
I need an FPGA board with a 64-bit 66MHz PCI bus and Linux drivers, and I need to be able to demo it, and I need it fast. If that's not demanding enough I can add more requirements. I have looked through 53 v...
skintigh_spam