VHDL for FPGA VME Slave 2 434 (8/15/2003 8:46:43 PM)
I'm working on a FPGA that is to have a few R/W registers on a VME bus. Anybody have some VHDL code they would like to share? If I use your ideas then your name will forever be in lights! Thanks! ...
Colin

Problem with Modelsim Lisence server... 3 136 (8/14/2003 1:41:39 PM)
Hi guys, Here i have a problem with my Modelsim lisence server.I have 2 lisences for modelsim in my office. But many a times if someone dont close the modelsim properly or dont release the lisence (by command q...
deb_astro

Data Structure Viewer 2 120 (8/12/2003 3:43:29 AM)
Data Structure Viewer is a GUI based tool written in Perl and Perl-Tk. It allows you to convert between a data structure (e.g. IPv4 header) and individual fields in the data structure by simple mouse clicks. It...
Jim

custom memory array implementaion 2 83 (8/17/2003 5:52:10 PM)
Hi Group, This is a question related to custom memory array implementaion. I need to implement two memory array which alternate for read and write according to the following: Writing input into Array: Ev...
kiran_krishna_choudh

Synthesisable fixed-point arithmetic package 1 116 (7/30/2003 2:01:03 PM)
Six months after I said "it's nearly done", I've now finished an alpha-test version of the synthesisable VHDL fixed-point package I promised. Doesn't time fly when you're enjoying yourself? :-) I've published...
Jonathan

Yet another modelsim problem 1 85 (8/12/2003 10:13:12 AM)
Completed process "Generate Post-Translate Simulation Model". ERROR: Hidden remap failed Reason: Launching Application for process "Simulate Post-Translate VHDL Model". not only the software's stupid eno...
Thomas

Limitations of Quartus II V3.0 Web 4 142 (8/13/2003 8:56:18 AM)
Hi guys, I'm trying to simulate a block-based design with Altera's Quartus II V3.0 Web version, however I cannot seem to simulate beyond 100ns irrespective of what end points I set for the default and for the ...
chris

Skew on a clock tree on a virtex II : what is the good figure ? 1 111 (8/13/2003 8:47:09 PM)
Hi, I am working on a design involving a virtex II -5. I read in a previous post that the skew one could expect from a clock tree is less than 100 ps. However when, on the design I am developping, I run the ti...
jean

Xilinx DLL driving multiple off chip clocks 3 117 (8/12/2003 9:51:38 PM)
I have the standard sort of circuit from the Xilinx App note driving an off chip clock:- Main clock comes onto chip through an IBUFG to CLKIN of the DLL CLK0 from the DLL is fed off the chip through an OBUFT....
Ken

PCI on Virtex II Pro (corrected) 0 116 (8/13/2003 5:35:02 PM)
Sorry, I just had to add which V2P device I am referring to: Hi, We are trying to implement the Xilinx 66/64 PCI core on a V2P20-5. Unfortunately, we just received a note from Xilinx that the -5 device will ...
tal