hidden remap failed 1 103 (7/5/2003 8:54:57 AM)
when trying to do a simulation, I get this: Completed process "Generate Post-Translate Simulation Model". ERROR: Hidden remap failed Reason: Launching Application for process "Simulate Post-Translate VHDL M...
Thomas

NIOS tutorial for the Stratix1S10 7 87 (7/2/2003 8:31:41 PM)
I'm trying to follow the NIOS tutorial for the Stratix1S10. At one point, page 16 of the 'tt_nios_hw_stratix_1s10.pdf' I should start the SOPC builder. A quick console window opens, to fast to recognize anythin...
tschaggelar (21)

Regarding NRZ 8 51 (7/2/2003 10:28:39 AM)
Hi everyone, Iam basic to the communication design, I have a query regarding NRZ interface with FPGA, Can we provide NRZ interface to FPGA, how does the voltage level will be at the interface ...
guest

test #2 0 132 (7/4/2003 5:11:27 PM)
can i post a message ...
seannstifler69

ARM+FPGA 1 108 (7/3/2003 6:06:26 AM)
Hello, I am looking for an ARM (preferably StrongARM) w/ FPGA development board. StrongARM preference is for mainly for Linux. Any other supported processor will do as well. Thanks a lot! -Sumeet ...
SP

okay what am I missing??? Please 0 93 (7/4/2003 1:56:43 AM)
Could someone please let me in on how the Flip Flops work in ISE Webpack schematics. Where is the Q/ . Do I simply run an inverter off from Q or what. Are these also global clk and rst or only if you assign the...
juice28

post-PAR simulation model 2 112 (7/3/2003 6:05:13 AM)
in ISE project navigator, when I run the 'generate post-PAR simulation model' process, I get a warning below: WARNING:NetListWriters:108 - In order to compile this verilog file successfully, please add $XILINX...
Jay

ACEX (EP1K) Power-Up Current 1 97 (7/3/2003 6:38:09 PM)
Since Altera seems to be active in this group, I will ask the question here. I have finally gotten an acceptable price on the EP1K30 part (5 volt tolerant) and will be using it in my design provided I don't st...
rickman

Questions about Design Compiler. 0 140 (7/3/2003 10:22:57 PM)
Hi, I'm new to Synopsys Design Compiler. I have some questions: 1. Should I always set drive strength and load driven by the ports before optmization? But I don't know what kind of value i can use and how to g...
Mike

Process variable setup times and propogations 5 113 (7/2/2003 6:52:46 PM)
Reposting: Sorry for the earlier mess. The Xilinx newsgroup portal apparently chewed my origional posting! Greetings folks, I am having a strange time with some code I recently wrote to implement a UART ...
Matt