division 5 108 (7/5/2003 5:30:54 AM)
hello there i am relatively new to VHDL..this might sound simple any ideas how to carry out division (floating point) in VHDL?? ...
ketone007sa

wired downloading bitstream to spartan2 2 98 (7/7/2003 11:58:17 PM)
HI, I have a Avnet Spartan2 board, if I download the the .mcs (prom file) comming with the board to it, it seems everything is OK. Then I build my design, went through the implementation flow, and I run a s...
Jimy

create JAM-File for Xilinx device 3 318 (7/3/2003 1:27:02 PM)
Hi there i'm currently trying to configure Alteras JAM Player for a Mitsubishi M16 Controller to program multi vendor device JTAG chains. Input files are either *.jam (JAM file) or *.jbc (JAM-ByteCode file). I...
christoph

Synplify and then Quartus 1 103 (7/9/2003 3:55:15 PM)
Hi, I have been using Quartus II 2.0 for all my synthesis and fitting needs for the APEX20KE device I have on my prototype board. I hear that Quartus is not an efficient synthesizer compared to Synplicity's Sy...
prashantj

Rant mode ON 10 76 (7/8/2003 3:48:28 PM)
I need to vent a little steam. So at risk of making myself look stupid (or more stupid) I will do it here. I have been trying to get the Quartus 3.0 software and a license since last Thursday. I tried thre...
rickman

Xilinx ISE drops support for more parts 30 111 (7/1/2003 12:47:25 PM)
I am reposting after a memo from reader siting problems using the Xilinx link to post to this group. Sorry about any problems this may have caused. After the release of Alliance 3 support was no longer offere...
lecroy7200

std_logic_vector type port doesn't work after synthesis. 3 97 (7/8/2003 12:05:13 AM)
Hi I encountered a problem during synthesis and I really hope I can get your help. I declared a std_logic_vector(7 downto 0) (inout type) entity port in my VHDL program. In the testbench, I will try to assign...
Mike

cascaded DLL's in VirtexE, routing problems 0 90 (7/9/2003 11:45:12 AM)
I do a rather heavy cascaded clock division/multiplication using DLL's in a VirtexE and have problems with routing resources from/to the dll's. I do not have enough resources to route all LOCKED signals through...
Morten

Xilinx price question 0 135 (7/9/2003 11:21:27 AM)
Hi, I've just had a look at marshall's (avnet) web site and it seems that the Xilinx Virtex II XC2VP100 is $11512. Did I miss something or lost some zeroes ? Is it that kind of price ? Thanks a lot for your co...
Mancini

Leonardo changes name of lpm megafunction 0 87 (7/9/2003 6:38:14 AM)
Hey, I'm trying to create a 20-bit pipelined adder using the lpm_add_sub megafunction, but when I try and compile my project in leonardo it changes the name in the .edf file from lpm_add_sub to lpm_add_sub_20_...
jaz_shnat