Digital Design with just one clock at one edge 6 82 (7/17/2003 6:01:14 AM)
Hi there! I hope this isn't too trivial: I'm having a digital system with a finite state machine and a few other modules which send a control signal to the FSM. Do you think it is possible to use only clock and...
Henning

Digital Root circuit using tree of 4-bit CLA's with Cout fed into Cin 3 107 (7/16/2003 5:57:30 PM)
Hi, In order to generate hexadecimal Digital Root of a number (i.e, sum-of-hexdigits until it reduces to a single hex number - a nibble) For e.g 0x123a = 0x1 + 0x2 +0x3 +0xa = 0x10 = 0x1 + 0x0 = 1 is the ...
lrl

Combinational logic and gate delays - Help 9 101 (7/13/2003 3:30:22 PM)
Hello All I have a combinational logic circuit generating a number of waveforms from the main clock input. There are a number of external inputs to this circuit controlling the turning on and off of different...
dgleeson-2 (18)

Fixed point signed multiplication algorithm 3 268 (7/2/2003 12:47:02 PM)
Hello, I am implementating Fixed point signed multiplication. Is there a algorithm to implement it. I have done the usual method of multiplication i.e partial products ...shift and add method. But its very slow...
praveenkumar1979

XML for VHDL documention and structural description of Hardware SoC 0 173 (7/11/2003 2:29:05 PM)
Hi VHDL GNU men, Amontec is interested to build an auto-documentation of our VHDL libraries, cell-by-cell. The documentation will stay basic, like : general description port description generic description i...
Amontec

how can I use a signal defined in one Architecture to another Architecture 4 98 (7/9/2003 5:51:52 PM)
Hello everybody, I want to use the signal defined in one architecture in VHDL to another architecture. I have two architecture in the same .vhd file and I am using Component mapping. I required the result of ...
kalimuddin

How to change Read Only Constraint to Read-Write 3 46 (7/9/2003 1:08:30 PM)
Hi, I am using singal of 32 bit's lenght in my .vhd file and I am compiling using Makefile. I have also defined a UCF file. My UCF file is generating error when run ngd build using Makefile. The error is given...
fpga_uk (2)

Make file ...........Help Please 1 81 (7/9/2003 5:19:09 PM)
Hi Fellows, How can I synthesize multiple file one by one using xilinx compiler in MAKEFILE script. I have done using only one file but when I enter multiple files in "VHDL= ....." field thenI get the followin...
vhdl_uk

phase noise in NCO 9 81 (7/8/2003 12:33:20 PM)
Hello, I want to make a phase measurement at 100MHz with a NCO at 200+ MHz This NCO will have a 32 bit phase accumulator and a 32 bits phase offset. The output will be only one bit. I will use a phase comparat...
Marc

PROM JTAG download cable for Xilinx Spartan II + Webpack 0 143 (7/10/2003 12:41:29 AM)
Hi, I have a PROM (XC18V02) set up on my Spartan IIE evaluation board. I'm developing under Xilinx ISE 5. I'm wondering what would be the simplest JTAG cable I could build (or buy if real cheap) to downloa...
gabsterblue (1)