interrupt handler for microblaze system 0 117 (11/19/2003 10:40:17 AM)
Hi, We have made our own opb slave which has an interrupt signal to the opb interrupt controller. In the mpd file you have to specify this signal with the options "level" or "edge" and "sigis=interrupt". In th...
Frank

XPS - Compiliing Core Generator's components 0 138 (11/19/2003 9:13:26 AM)
Hi all, How do I compile components created with CoreGenerator in XPS. Thanks, Arkaitz. ...
arkagaz

HDL-Designer 2002: cannot edit generic mapping in Block-Diagram-view 3 116 (11/18/2003 3:48:10 PM)
Hallo to all. While I'm designing a new component in a block diagram view, I have to instantiate another component and have to edit the generic value of this instantiated component. If I want to edit it direc...
peter

Active-HDL 6.1 pricing 14 153 (11/17/2003 11:24:06 AM)
Hi, Does anyone know how much Aldec Active-HDL 6.1 costs? I emailed Aldec, but they didn't bother to reply. Regards, Allan. ...
Allan

Do I need to connect all Vref in a bank together? 12 73 (11/15/2003 1:10:04 AM)
Spartan 2 datasheet says Vrefs are internally connected, but must also be externally connected. Is this really needed if you only use one input? ...
pNaonStpealmtje (186)

Xilinx DCM LOCKED signal valid after input clock returns? 1 238 (11/18/2003 11:39:24 PM)
OK, the DCM input clock goes away, and I understand the LOCKED signal is not valid. After the input clock comes back, can you rely on the LOCKED signal to indicate that a DCM reset pulse is needed? And ditto ...
barry_brown (3)

xilinx platform flash question 1 104 (11/18/2003 3:30:29 AM)
I need to configure an XC2V6000 from flash. Planning to use six XCF04S PROMs, but I have a few questions. 1. Anyone having problems buying these PROMs? Avnet had some in stock last week, but today they had non...
Robert

CFP: EH-2004 Second Call for Abstracts 0 54 (11/18/2003 9:45:58 PM)
Dear Colleague, The abstract submission deadline (December 1st, 2003) for the 2004 NASA/DoD Conference on Evolvable Hardware is now approaching. The main purpose of the one-page abstract is to provide the auth...
eh-2004

Xilinx UART Macro ERROR??? 5 109 (11/13/2003 9:30:26 PM)
Hello, We have recently been using the free Xilinx UART macro with the 16-byte FIFO (from app note XAPP223) in a design, instantiated in a Virtex XC2V1000. We are using both the Rx and Tx macros (actually, 32 ...
john

SRL16 as synchronizer 9 87 (11/17/2003 7:45:37 AM)
Hello All, I'm wondering, if it's possible to use SRL16s to synchronize external signals to your clock. If I do the standard thing in VHDL, e.g. a couple of assignments in a clocked process, then XST gives me...
hjdorn (1)