how to protect own IP in Xilinx ISE1198 (8/4/2003 7:10:19 PM) Hello, Is there a way to put a ready developed VHDL code into binary form, so that other can use, but not read it? Of course there is such a way, because the IP vendors live from that :-). Does anyone know h... Guenter
opencores.org - Question on project licensing?689 (8/3/2003 11:26:16 PM) I would like to contribute a multi-cycle (slow, but area-compact) (Hehe, someone else already released a pipelined integer-divider, to the opencores.org repository. Gence I'm marketing my divider as 'compact'!... Pacbell
interface with 860094 (8/4/2003 2:54:00 PM) Hi all, Could any one tell me where I can find a sample VHDL code for interfacing a Motorola MPC860 (External Bus Operation : Single-Beat Transferts and Burst Transferts) with a FPGA ?. Thanks lot in advanc... peter_b
Multiple clock generations098 (8/4/2003 12:41:12 PM) I want to generate clocks of different frequencies of 150 Mhz, 38 Mhz, 8Khz from a clock of frequency 2048KHz. The factor comes out to be very odd. Can anyone please suggest me how can I do that? Regards Mo... monibkhan
Question: String matching with CAM?196 (7/31/2003 9:28:01 PM) Has anyone used Content Addressable Memory to perform string matching? I don't know much of anything about CAM, but I can imagine it would be much more flexible than hard-coding the strings I want to search fo... skintigh_spam
Downloading into XCV6000100 (7/31/2003 11:32:55 AM) Hi Fellows, I have main architecture consists of different components. All these components are defined in different *.vhd files and I am combining all these VHDL files in one *.vhd file and downloading into t... fpga_uk
GL85 synthesizable code287 (7/25/2003 10:24:10 AM) Hi, VHDL friends Does anyone have a synthesizable gl85, or i8085 VHDL design? I have them, but can't synthesize with leonardo or synopsis. Please reply to this address. Thank you a lot! ... Saeed
Relative placement constraints in VHDL for Virtex multipliers1101 (7/25/2003 8:28:58 AM) This question may have been asked before but ... I often have timing problems when using virtex-II dedicated multipliers. After synthesis/P&R I have fixed these by looking at the placement with ISE floorplanne... bymanaar
Phase / frequency detector types7104 (7/19/2003 9:48:32 AM) Hi all. I am attempting to design an All-Digital Phase Lock Loop for a motor control application. I know it's been done before, and I might even find an off the shelf part that does close to what I want, but... Jay