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```Hello

I wrote a vhdl code for implementing amplifer and ADC on sparan3E board, I
am working with LTC1407A-1 Dual A/D on spartan3E(with SPI protocol),my
problem is when I changed the analog voltage which is applied to this
A/D,the eight most significant digital value on LEDs also changed
accordingly,but it's not equal to what I calculated based on the formula
D[13:0]=(Gain*(Vin-1.65)*8192)/1.25v provided in the data sheet.LED's
follow specific pattern for each analog voltage ,I mean I tested different
voltage and every time the result on LED's were same,so my program does
understand different volages,but the problem is ,it is not equivalent to
what I got from formula. can anyone help?please give me an idea what I can
do.

```
 0

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```On Wed, 30 Dec 2009 14:36:19 -0600, "mlajevar" wrote:

>I wrote a vhdl code for implementing amplifer and ADC on sparan3E board, I
>am working with LTC1407A-1 Dual A/D on spartan3E(with SPI protocol),my
>problem is when I changed the analog voltage which is applied to this
>A/D,the eight most significant digital value on LEDs also changed
>accordingly,but it's not equal to what I calculated based on the formula
>D[13:0]=(Gain*(Vin-1.65)*8192)/1.25v provided in the data sheet.LED's
>follow specific pattern for each analog voltage ,I mean I tested different
>voltage and every time the result on LED's were same,so my program does
>understand different volages,but the problem is ,it is not equivalent to
>what I got from formula. can anyone help?please give me an idea what I can
>do.

First you can start to be a scientist :-)

Sure it's not equivalent to the formula.  Shit happens.  But
what IS it?  Is it linear?  Is it monotonic?  Have you graphed it?
You say it's repeatable, so surely you can do that.  The formula
you quote depends on the values of reference voltages; are they
set correctly?  Where do they come from?  Have you used the correct
filtering and grounding, as indicated in the device data sheet?

Engage brain, and enlightenment often follows.
--
Jonathan Bromley
```
 0

```On Dec 30, 3:36=A0pm, "mlajevar" <mahsa_lajeva...@yahoo.com> wrote:

> please give me an idea what I can do.

1. Use either an oscilloscope or a multi-meter to make a measurement
2. If #1 checks out, run a simulation and verify correct operation of

This basic process works to solve most any design problem.  If you're
stumped and have no hypothesis to explain the unwanted behavior, then
you make measurements to give you additional insight (#1), or run
additional simulation test cases (#2) until you finally can say 'Ah
ha!'...then you fix whatever it was that caused you to say 'Ah ha!'

Kevin Jennings

```
 0

```Hello

I did the simulation for amplifier part to check if SPI communication
working properly or not,and it was right,after that I made a op level
module from my amplifier combined with ADC behavior which I cannot simulate
it ,because t needs analog voltage,so all I can do for the top level is to
check it when it is programmd on the board.

Moreover,the reference volatge generated via a voltage divider on the
board,I just applied 3.3 volt from power supply to vcc og Header J7,so I
suppose reference voltage should be right.

the thing is what I got from LEDs is not even two's complement or invert
form of what I expected from formula. with these information,does any one
have new idea? thanks in advance

---------------------------------------
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com
```
 0

```On Dec 30, 11:43=A0pm, "mlajevar" <mahsa_lajeva...@yahoo.com> wrote:
> I did the simulation for amplifier part to check if SPI communication
> working properly or not,and it was right,after that I made a op level
> module from my amplifier combined with ADC behavior which I cannot simula=
te
> it ,because t needs analog voltage,

VHDL has a data type 'real', analog voltages can be modelled quite
easily.

To simulate the ADC, make an entity with all of the I/O using type
finally implement the SPI interface of the ADC.  Do all of this by
consulting the data sheet for the part.  Now you have a simulation
model for the ADC that will work with your design.  Beef up your
testbench for your FPGA to include the ADC model and some form of
stimulus (even a constant voltage) for the ADC input.

> so all I can do for the top level is to
> check it when it is programmd on the board.
>

If the problem is actually in the VHDL code that you wrote, then
checking it on the board is doing it the hard way.  If the problem is
in the analog portion of the board then a meter or scope is all you
should need to find the problem.  Looking at LED patterns is like
looking at Christmas lights and provides little information about the
problem unless it was something simple like the LED values represent
1/2 or 2x the correct value or some simple to spot thing like that.

> Moreover,the reference volatge generated via a voltage divider on the
> board,I just applied 3.3 volt from power supply to vcc og Header J7,so I
> suppose reference voltage should be right.
>

Suppose all you want...I suggested to measure and verify so that you
wouldn't have to speculate and guess.

> the thing is what I got from LEDs is not even two's complement or invert
> form of what I expected from formula. with these information,does any one
> have new idea? thanks in advance =A0 =A0 =A0 =A0 =A0
>

It's not at all clear just what you know is working and what is not.
It sounds like you wrote some VHDL and the logic is being implemented
in some board that has a Spartan 3E on it.  Is the board design in
question or is it the VHDL that controls the ADC?  Or maybe the LED
driver?  If the board is in question then the meter on the analog
signals will clear it all up.  Once you've verified that the inputs to
the ADC are correct, then guess what, the problem is in your VHDL
code...and simulation will find it...IF you model the system correctly
(i.e. the above mentioned ADC model has been verified to the data
sheet for the part, the interconnect from ADC to Spartan is correct,
the interconnect between Spartan and LEDs are modelled correctly)

Kevin Jennings
```
 0

```Hello

I got that the values on LEDs is the half of the value I expect from the
formula,so I think the problem would be with the 14th bit in my vhdl
code,because from 13th bit to LSB ,all bits are almost same,but the big
differencce comes from being half of the original value caused by 14th
bit.

I am trying to work with chipscope,I haven't worked with it ,and I don't
know which type of chipscop pro  have to work
with?(ATC2,ICON,ILA,VIO)according to some materials I read,I think I should
work with ILA s that right? I mean to check all my fourtheen bits value for

---------------------------------------
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com
```
 0

```On Jan 6, 2:18=A0pm, "mlajevar" <mahsa_lajeva...@yahoo.com> wrote:
>
> I got that the values on LEDs is the half of the value I expect from the
> formula,so I think the problem would be with the 14th bit in my vhdl
> code,because from 13th bit to LSB ,all bits are almost same,but the big
> difference comes from being half of the original value caused by 14th
> bit.

Keep in mind that on a serial interface being off by a factor of two
in your read value is the same as having the value off by one clock in
the serial domain.  Perhaps you're actually missing the least
significant bit!
```
 0

```>On Jan 6, 2:18=A0pm, "mlajevar" <mahsa_lajeva...@yahoo.com> wrote:
>>
>> I got that the values on LEDs is the half of the value I expect from
the
>> formula,so I think the problem would be with the 14th bit in my vhdl
>> code,because from 13th bit to LSB ,all bits are almost same,but the big
>> difference comes from being half of the original value caused by 14th
>> bit.
>
>Keep in mind that on a serial interface being off by a factor of two
>in your read value is the same as having the value off by one clock in
>the serial domain.  Perhaps you're actually missing the least
>significant bit!
>

From experience, this is an all-too-common problem with SPI and other
serial interfaces...

---------------------------------------
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com
```
 0

```can i have ur vhdl code ...wid appreciate it a lot ...
my gmail:zakaria.nits@gmail.com```
 0

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