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```Dear Group,

I have a xilinx xc9536 , a 22 bit counter, and a 5 bit counter.
The 22 bit counter is used as a 48mhz clock divider for the
other 5 bit counter, hence bit 22 is used as humanly visible
clock. The counter stops when it reaches 11111.
The problem I am having is that when I apply my digital
multi meter to the pins of the counter to check if the count
has finished, then the counter seems to suddenly start
counting again. I also noticed that if before applying the
multimeter I disconnect the oscillator from the chip this will
not happen, so it seems the oscillator is making the design
unstable. Any ideas?
Also, as a beginner, which book do I need to understand
the tricks and quirks of xc9536 high speed design. Should
I be designing on a behavioural level, or should I use low
level?

My clock code is as follows

reg [21:0] nn;
assign cdiv= nn[21];
always @(posedge c0)
nn=nn+1;

my other clock goes like this

always @(posedge clock or posedge reset1)
begin
if (reset1)
aa <= 0;
else aa <= aa + 1;
end

The clocks are physically connected from external pins with a wire.
For the oscillator I use gck1.

Many thanks.

```
 0

See related articles to this posting

```> The problem I am having is that when I apply my digital
> multi meter to the pins of the counter to check if the count
> has finished, then the counter seems to suddenly start
> counting again. I also noticed that if before applying the

48 MHz ? With a multimeter ?

Just solder a LED instead... or put a resistor at the end of your
probe... resistor scope probe is THE low-tech low-cost "but it works!" way
for high speed probing ;)

A few possible causes :

- you're wearing wool or something and generate enough static electricity
to zap the circuits ; ground yourself properly before it costs you a
replacement board
- the parasitic cap of the probe is enough to cause mayhem, ringing, etc

> multimeter I disconnect the oscillator from the chip this will
> not happen, so it seems the oscillator is making the design
> unstable. Any ideas?

Well, without clock, all synchronous logic is on blind-deaf mode, and you
used synchronous logic for your counter, so...
```
 0

```Dear User,

> 48 MHz ? With a multimeter ?
>
> Just solder a LED instead... or put a resistor at the end of your
> probe... resistor scope probe is THE low-tech low-cost "but it works!" way
> for high speed probing ;)
>

I do use a led, and this is why I divide the clock with 22 bits, so I can
actually see the led flashing with different speeds on different counter
pins.

> A few possible causes :
>
> - you're wearing wool or something and generate enough static electricity
> to zap the circuits ; ground yourself properly before it costs you a
> replacement board
> - the parasitic cap of the probe is enough to cause mayhem, ringing, etc
>
> > multimeter I disconnect the oscillator from the chip this will
> > not happen, so it seems the oscillator is making the design
> > unstable. Any ideas?
>
> Well, without clock, all synchronous logic is on blind-deaf mode, and you
> used synchronous logic for your counter, so...

Yes, this is silly of me, of course without a clock it cannot move.

I was just wondering if there were any special checks I should make
because I am using 50mhz. I think I can use a PIC to simulate a slower
clock, I'll try that.

And I forgot to mention as well that I have a "done" pin, which goes high
when counter reaches "11111". Again, if I touch that pin with a led it will
start counting again. This register actually controlls if the clock is
multiplexed into the divider counter, when done=1 it stops the oscillator
from
reaching the divider. Clearing it would cause the counter to continue.

Maybe when I touch the "done" pin with a led it acts as a momentary
short ground. I can't think why that would be, my led is very low current,
it is limitted with a relatively large 10K.

I also have some other inputs, which once the clock is on 11111 should
not make any difference, but again if I touch them with a led, or even
just leave them floating, the counter starts to count again.

```
 0

```> I was just wondering if there were any special checks I should make
> because I am using 50mhz. I think I can use a PIC to simulate a slower
> clock, I'll try that.

I hate to ask the obvious - but have you simulated the design at this
clock rate? I haven't used the xc95xx stuff but certainly when I use a
Spartan, simulation is the key to making a deisgn that does what I
want it - and if it works, it narrows any problems to the hardware.

```
 0

```Tonico wrote:
> Dear Group,
>
> I have a xilinx xc9536 , a 22 bit counter, and a 5 bit counter.
> The 22 bit counter is used as a 48mhz clock divider for the
> other 5 bit counter, hence bit 22 is used as humanly visible
> clock. The counter stops when it reaches 11111.
> The problem I am having is that when I apply my digital
> multi meter to the pins of the counter to check if the count
> has finished, then the counter seems to suddenly start
> counting again. I also noticed that if before applying the
> multimeter I disconnect the oscillator from the chip this will
> not happen, so it seems the oscillator is making the design
> unstable. Any ideas?
<snip>

Do you use bypass capacitors from power to ground?
```
 0

```On Jul 25, 5:30 am, <Tonico> wrote:
> Dear Group,
>
> I have a xilinx xc9536 , a 22 bit counter, and a 5 bit counter.
> The 22 bit counter is used as a 48mhz clock divider for the
> other 5 bit counter, hence bit 22 is used as humanly visible
> clock. The counter stops when it reaches 11111.
> The problem I am having is that when I apply my digital
> multi meter to the pins of the counter to check if the count
> has finished, then the counter seems to suddenly start
> counting again. I also noticed that if before applying the
> multimeter I disconnect the oscillator from the chip this will
> not happen, so it seems the oscillator is making the design
> unstable. Any ideas?
> Also, as a beginner, which book do I need to understand
> the tricks and quirks of xc9536 high speed design. Should
> I be designing on a behavioural level, or should I use low
> level?
>
> My clock code is as follows
>
> reg [21:0] nn;
> assign cdiv= nn[21];
> always @(posedge c0)
>   nn=nn+1;
>
> my other clock goes like this
>
> always @(posedge clock or posedge reset1)
>   begin
>     if (reset1)
>         aa <= 0;
>     else aa <= aa + 1;
>   end
>
> The clocks are physically connected from external pins with a wire.
> For the oscillator I use gck1.
>
> Many thanks.

I don't quite understand Verilog, but I don't see that the output of
you have something like:
if cdiv = 1
aa <= aa + 1;

-Dave Pollum

```
 0

```> <snip>
>
> Do you use bypass capacitors from power to ground?

I do have one 0.1 uF multi layered ceramic (dipped) on the power/gnd
pins on the right facet.

```
 0

```>
> I hate to ask the obvious - but have you simulated the design at this
> clock rate? I haven't used the xc95xx stuff but certainly when I use a
> Spartan, simulation is the key to making a deisgn that does what I
> want it - and if it works, it narrows any problems to the hardware.
>

Is this modelsim?

```
 0

```I've done "Simulate Behavioural Model" from the ISE, it worked.

```
 0

```BTW
I had to reduce the divider counter to 1 bit, otherwise  there are
4 million simulation steps per second timer clock.

```
 0

```> I don't quite understand Verilog, but I don't see that the output of
> your 22-bit counter has any affect on your 5-bit counter.  Shouldn't
> you have something like:
>   if cdiv = 1
>     aa <= aa + 1;

Sorry, posted wrong code, here is the correct code

`timescale 1ns / 1ps

module counter (
input wire c0,
input wire c1,
output reg [5:0] aa,
output wire cdiv
);

reg [21:0] nn;
assign cdiv= nn[21];

always @(posedge c0)
nn=nn+1;

always @(posedge c1)
aa <= aa + 1;

endmodule

```
 0

```> Sorry, posted wrong code, here is the correct code
>
> `timescale 1ns / 1ps
>
> module counter (
>   input wire c0,
>   input wire c1,
>     output reg [5:0] aa,
>   output wire cdiv
>     );
>
>   reg [21:0] nn;
>   assign cdiv=3D nn[21];
>
>   always @(posedge c0)
>   nn=3Dnn+1;

Shouldn't this be a "<=3D" ?

>   always @(posedge c1)
>   aa <=3D aa + 1;
>
> endmodule

Well, you have various options :

- your verilog code is wrong (ie it compiles but it doesn't do what you=
=

think) : check your compilation warnings.
- you have a gremlin (signal integrity problem, ground bounce...) then =
=

=

image sharing site and put the link here.
```
 0

```Another problem (less serious), while programming the device,
if I leave the oscillator connected the programmer fails, whereas
if I revice the oscillator it works. (funny?)

Another clue, I use the power supply from my usb port as I haven't
got a dedicated 5V supply, measuring the voltage near the device
reads 4.75v and current through device is 70mA without oscillator
and 85mA with oscillator.

"PFC" <lists@peufeu.com> wrote in message news:op.tv04bwlmcigqcu@apollo13...
> Sorry, posted wrong code, here is the correct code
>
> `timescale 1ns / 1ps
>
> module counter (
>   input wire c0,
>   input wire c1,
>     output reg [5:0] aa,
>   output wire cdiv
>     );
>
>   reg [21:0] nn;
>   assign cdiv= nn[21];
>
>   always @(posedge c0)
>   nn=nn+1;

Shouldn't this be a "<=" ?

>   always @(posedge c1)
>   aa <= aa + 1;
>
> endmodule

Well, you have various options :

- your verilog code is wrong (ie it compiles but it doesn't do what you
think) : check your compilation warnings.
- you have a gremlin (signal integrity problem, ground bounce...) then
image sharing site and put the link here.

```
 0

```
Tonico wrote:
> Another problem (less serious), while programming the device,
> if I leave the oscillator connected the programmer fails, whereas
> if I revice the oscillator it works. (funny?)
>
Ummm, this STRONGLY suggests a noisy power supply, insufficient bypass
caps, too much lead/trace inductance on that one sole cap, or something
like that.

> Another clue, I use the power supply from my usb port as I haven't
> got a dedicated 5V supply, measuring the voltage near the device
> reads 4.75v and current through device is 70mA without oscillator
> and 85mA with oscillator.
Something horrible I just found out is that the current consumption equation
in the XC95xx datasheets are wildly wrong.  It depends on how much
combinatorial logic you have implemented in the macrocells, I just did
a very dense CPLD.  Xilinx has admitted that the current consumption
can be 2-3 times higher than that equation gives!  With the macrocells
in high-power mode, I was getting about 112 mA on a 9536!  With all of
them in low-power (my clock is 10 MHz, so I can get away with that) it
drops to "ONLY" 72 mA, while the equation gives 30!

If the operation of FF and logic on chip prevents programming, then it
is almost certain that either the switching is creating noise due to
insufficient capacitance, or the increased current draw is pulling the
supply voltage too low.  I suspect the former, the voltage tolerance
seems to be pretty wide.

Jon

```
 0

```<Tonico> wrote in message news:46a72647\$1_2@mk-nntp-2.news.uk.tiscali.com...
> Dear Group,
>
> I have a xilinx xc9536 , a 22 bit counter, and a 5 bit counter.
> The 22 bit counter is used as a 48mhz clock divider for the
> other 5 bit counter, hence bit 22 is used as humanly visible
> clock. The counter stops when it reaches 11111.
> The problem I am having is that when I apply my digital
> multi meter to the pins of the counter to check if the count
> has finished, then the counter seems to suddenly start
> counting again. I also noticed that if before applying the
> multimeter I disconnect the oscillator from the chip this will
> not happen, so it seems the oscillator is making the design
> unstable. Any ideas?
<snip>

Are you using flying leads with a breadboard?  PC layoud with solid ground
planes?  Even though you may be using a 5V device with a 5V oscillator, you
may be getting severe overshoot and undershoot on the clock.  If you have a
long, flying lead, consider substituting a twisted pair with the clock and
ground on the two wires from the oscillator to the CPLD's clock input.
Adding a series resistor at the oscillator output around 100 ohms may make
the destination clock look even prettier.

You only have the one clock destination, correct?

Please verify that you have some bulk capacitance (10uF or larger) somewhere
on this side of the USB "power supply" entry to your circuit.

```
 0

```> Are you using flying leads with a breadboard?  PC layoud with solid ground
> planes?  Even though you may be using a 5V device with a 5V oscillator,
you
> may be getting severe overshoot and undershoot on the clock.  If you have
a

I didn't say I have a 5V oscillator, I have i 48mhz oscillator, I assume it
is suitable as it is working. The oscillator is 68x7208 48.0mhz 8931 ndk
japan.

> long, flying lead, consider substituting a twisted pair with the clock and
> ground on the two wires from the oscillator to the CPLD's clock input.
> Adding a series resistor at the oscillator output around 100 ohms may make
> the destination clock look even prettier.
>
> You only have the one clock destination, correct?
>
> Please verify that you have some bulk capacitance (10uF or larger)
somewhere
> on this side of the USB "power supply" entry to your circuit.

Good, I added this, and will shortly try again, maybe it will solve the
problem.
Added 10uF electrolitic + 4.7uF tantalum.

>
>

```
 0

```How do I check this?

```
 0

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