I am trying to minimize my bram usage for the design. My basic BRAM
code in vhdl is shown below. If I change the address width to 8 and
data width to 64 the synplify pro gives me 2 brams usage. Shouldnt it
be only one BRAM since I am using 256 * 64 = 16384 bits? Am I doing
something wrong in the vhdl code?
Appreciate any help.
Thanks.
ENTITY SDP_8_8192 Is
	GENERIC(AWIDTH : INTEGER := 8; DWIDTH : INTEGER := 64);
PORT(
	CLK : IN std_logic;	WE : IN std_logic;	ADDRA  :  IN std_logic_vector
(AWIDTH-1 downto 0);
	ADDRB  :  IN std_logic_vector(AWIDTH-1 downto 0);
	DIA    : IN std_logic_vector(DWIDTH-1 downto 0);
    DOB   :  OUT std_logic_vector(DWIDTH-1 downto 0)
);
end entity;

architecture synth of SDP_8_8192 is

    constant MEM_DEPTH   : integer := 2**AWIDTH;
    type mem_array is array(0 to MEM_DEPTH-1) of std_logic_vector
(DWIDTH-1 downto 0);
    signal ram           : mem_array;
 begin
   proc: process(CLK)
    begin
       if rising_edge(CLK) then
          if WE = '1' then
             ram(conv_integer(ADDRA)) <= DIA;
          end if;
            DOB <= ram(conv_integer(ADDRB));
       end if;
    end process;

    END synth;

I would think it will depend on the fpga technology you are targeting as
the BRAM can have different port widths and sizes. Check with the user
guide for the fpga you are using.

Jon 	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

On Dec 5, 4:38=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote:
> I would think it will depend on the fpga technology you are targeting as
> the BRAM can have different port widths and sizes. Check with the user
> guide for the fpga you are using.
>
> Jon =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> This message was sent using the comp.arch.fpga web interface onhttp://www=
..FPGARelated.com

I am using virtex II pro x2vp70.I will check it out.

On Dec 5, 10:49=A0am, ni <nbg2...@gmail.com> wrote:
> On Dec 5, 4:38=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote:
>
> > I would think it will depend on the fpga technology you are targeting a=
s
> > the BRAM can have different port widths and sizes. Check with the user
> > guide for the fpga you are using.
>
> > Jon =A0 =A0 =A0 =A0
>
> > --------------------------------------- =A0 =A0 =A0 =A0
> > This message was sent using the comp.arch.fpga web interface onhttp://w=
ww.FPGARelated.com
>
> I am using virtex II pro x2vp70.I will check it out.

Virtex II maximum data width for a single BRAM is 36 bits.
However if you are careful, you can get a single-ported
BRAM of 72-bits by using both ports of the same BRAM
and tying off the upper address bit to 0, 1 for each
respective port.  For dual-port applications the limit
is 36 bits.  By the way using a BRAM at maximum width
and dual port uses all the routing resources to the
BRAM as well as the adjacent multiplier, so you will
lose the use of the multiplier.

Regards,
Gabor

On Dec 5, 11:07=A0am, Gabor <ga...@alacron.com> wrote:
> On Dec 5, 10:49=A0am, ni <nbg2...@gmail.com> wrote:
>
> > On Dec 5, 4:38=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote:
>
> > > I would think it will depend on the fpga technology you are targeting=
 as
> > > the BRAM can have different port widths and sizes. Check with the use=
r
> > > guide for the fpga you are using.
>
> > > Jon =A0 =A0 =A0 =A0
>
> > > --------------------------------------- =A0 =A0 =A0 =A0
> > > This message was sent using the comp.arch.fpga web interface onhttp:/=
/www.FPGARelated.com
>
> > I am using virtex II pro x2vp70.I will check it out.
>
> Virtex II maximum data width for a single BRAM is 36 bits.
> However if you are careful, you can get a single-ported
> BRAM of 72-bits by using both ports of the same BRAM
> and tying off the upper address bit to 0, 1 for each
> respective port. =A0For dual-port applications the limit
> is 36 bits. =A0By the way using a BRAM at maximum width
> and dual port uses all the routing resources to the
> BRAM as well as the adjacent multiplier, so you will
> lose the use of the multiplier.
>
> Regards,
> Gabor

Is there any application note which explains this stuff?
I am more interested in optimizing bram usage for my architecture.

ni wrote:

> Is there any application note which explains this stuff?
> I am more interested in optimizing bram usage for my architecture.

I use a vhdl or verilog block ram template for the size I want,
run synthesis, and look at the block ram utilization.


        -- Mike Treseler

On Dec 7, 12:48=A0pm, Mike Treseler <mtrese...@gmail.com> wrote:
> ni wrote:
> > Is there any application note which explains this stuff?
> > I am more interested in optimizing bram usage for my architecture.
>
> I use a vhdl or verilog block ram template for the size I want,
> run synthesis, and look at the block ram utilization.
>
> =A0 =A0 =A0 =A0 -- Mike Treseler

Running synthesis, translate, map, etc. is how I found out about
these quirks of architecture, but if you dig deep into the User
Guide (not the datasheet) you'll find this information.
Unfortunately the datasheet / user guide approach almost always
overloads you with so much information you're bound to miss
something that could be a showstopper for a board-level design
completed before the guts of the FPGA are designed.  In a
similar Virtex II design I found out I couldn't use all of
my DQ lines for a DDR SDRAM because of clock routing limitations
to adjacent IOB's.  This was before MIG was around to help you
find workable pinouts up front.  I had paired some DQ pins
with DQS pins and run out of clock routes because of the
DDR routing being shared with the adjacent IOB of a pair.
So my 64-bit wide SO-DIMM became a 59-bit wide memory.  The
lesson seems to be that if all possible get a workable design
going in the FPGA before board layout.

Regards,
Gabor