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### BUFGMUX placement

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while synthetising (with is10.1) leon3 processor for xilinx 3adsp1800
starter kit, I got this error :

Place:848 - Automatic clock placement failed. Please attempt to
analyze
the global clocking required for this design and either lock the
clock
placement or area locate the logic driven by the clocks so that
that the
clocks may be placed in such a way that all logic driven by them
may be
routed. The main restriction on clock placement is that only one
clock output
signal for any competing Global / Side pair of clocks may enter any
region.
For further information see the "Quadrant Clock Routing" section in
the

The competing Global / Side clock buffers for this device are as
follows:
BUFGMUX_X2Y1 :    BUFGMUX_X0Y2
BUFGMUX_X2Y0 :    BUFGMUX_X0Y3
BUFGMUX_X1Y1 :    BUFGMUX_X0Y4
BUFGMUX_X1Y0 :    BUFGMUX_X0Y5
BUFGMUX_X2Y11 :    BUFGMUX_X0Y6
BUFGMUX_X2Y10 :    BUFGMUX_X0Y7
BUFGMUX_X1Y11 :    BUFGMUX_X0Y8
BUFGMUX_X1Y10 :    BUFGMUX_X0Y9
BUFGMUX_X2Y1 :    BUFGMUX_X3Y2
BUFGMUX_X2Y0 :    BUFGMUX_X3Y3
BUFGMUX_X1Y1 :    BUFGMUX_X3Y4
BUFGMUX_X1Y0 :    BUFGMUX_X3Y5
BUFGMUX_X2Y11 :    BUFGMUX_X3Y6
BUFGMUX_X2Y10 :    BUFGMUX_X3Y7
BUFGMUX_X1Y11 :    BUFGMUX_X3Y8
BUFGMUX_X1Y10 :    BUFGMUX_X3Y9

I am new to quadrant clock constraint, can somebody provide help to
manualy place the BUFGMUXes...

regards


 0
Reply rponsard (31) 12/12/2008 10:19:42 PM

See related articles to this posting

Hi Raph,
My advice is to try to use fewer global clocks. Consider using a single fast
clock with clock enables for your slower clocked FFs, BlockRAMs etc.
HTH., Syms.

"raph" <rponsard@gmail.com> wrote in message
> while synthetising (with is10.1) leon3 processor for xilinx 3adsp1800
> starter kit, I got this error :
>
>
> Place:848 - Automatic clock placement failed.


 0

Hi Raph,

I suggest checking your Leon3 configuration. It is likely that you
have a ASIC configuration with clock-gating. When targeting an FPGA, I
believe you should get a single clock per core.

- gael

 0

thanks for your replies but it is not that...
if you are interested see :

http://tech.groups.yahoo.com/group/leon_sparc/message/14447

On Dec 15, 3:55=A0pm, Gael Paul <gael.p...@gmail.com> wrote:
> Hi Raph,
>
> I suggest checking your Leon3 configuration. It is likely that you
> have a ASIC configuration with clock-gating. When targeting an FPGA, I
> believe you should get a single clock per core.
>
> =A0- gael


 0

On Dec 12, 11:19 pm, raph <rpons...@gmail.com> wrote:
> while synthetising (with is10.1) leon3 processor for xilinx 3adsp1800
> starter kit, I got this error :
>
>  Place:848 - Automatic clock placement failed. Please attempt to
> analyze
>    the global clocking required for this design and either lock the
> clock
>    placement or area locate the logic driven by the clocks so that
> that the
>    clocks may be placed in such a way that all logic driven by them
> may be
>    routed. The main restriction on clock placement is that only one
> clock output
>    signal for any competing Global / Side pair of clocks may enter any
> region.
>    For further information see the "Quadrant Clock Routing" section in
> the
>
>    The competing Global / Side clock buffers for this device are as
> follows:
>    BUFGMUX_X2Y1 :    BUFGMUX_X0Y2
>    BUFGMUX_X2Y0 :    BUFGMUX_X0Y3
>    BUFGMUX_X1Y1 :    BUFGMUX_X0Y4
>    BUFGMUX_X1Y0 :    BUFGMUX_X0Y5
>   BUFGMUX_X2Y11 :    BUFGMUX_X0Y6
>   BUFGMUX_X2Y10 :    BUFGMUX_X0Y7
>   BUFGMUX_X1Y11 :    BUFGMUX_X0Y8
>   BUFGMUX_X1Y10 :    BUFGMUX_X0Y9
>    BUFGMUX_X2Y1 :    BUFGMUX_X3Y2
>    BUFGMUX_X2Y0 :    BUFGMUX_X3Y3
>    BUFGMUX_X1Y1 :    BUFGMUX_X3Y4
>    BUFGMUX_X1Y0 :    BUFGMUX_X3Y5
>   BUFGMUX_X2Y11 :    BUFGMUX_X3Y6
>   BUFGMUX_X2Y10 :    BUFGMUX_X3Y7
>   BUFGMUX_X1Y11 :    BUFGMUX_X3Y8
>   BUFGMUX_X1Y10 :    BUFGMUX_X3Y9
>
> I am new to quadrant clock constraint, can somebody provide help to
> manualy place the BUFGMUXes...
>
> regards

Try using a Xplorer script. It helps me when I encounter this problem
in EDK.

 0

Raph,

Yes it is. You're using too many clocks. If you insist on using all these
clocks, you are on the way to destruction. (BTW, I spent 2 seconds
googling - how to do fpga clocking - and found an apparently decent article
explaining why this is true. You did google for an answer, right? Maybe not,
http://www.design-reuse.com/articles/4854/fpga-clock-schemes.html)

Whatever, I suggest you RTM.
http://www.xilinx.com/support/documentation/user_guides/ug331.pdf
Try the section "Quadrant Clock Routing", like you were told to do in the
original error message.
Finally, if you post again, tell us specifically for what you're using each
of all these clocks, and ask questions about what you don't understand in
Good luck, Symon.

raph wrote:
> thanks for your replies but it is not that...
> if you are interested see :
>
> http://tech.groups.yahoo.com/group/leon_sparc/message/14447
>
> On Dec 15, 3:55 pm, Gael Paul <gael.p...@gmail.com> wrote:
>> Hi Raph,
>>
>> I suggest checking your Leon3 configuration. It is likely that you
>> have a ASIC configuration with clock-gating. When targeting an FPGA,
>> I believe you should get a single clock per core.
>>
>> - gael


 0

leon3 is a 32 bit softprocessors (see www.gaisler.com, part of grlib,
a complete IP library (amba bus for ddr, ddr2, eth, vga, usb, ...), so
it is a rather big design , IMHO very well done, and this bufgmuxes
are not useless...

people at gaisler do provide (all is opensource) implementations for
xilinx starter kits (spartan 3E1600 and 3Adsp18000) but their test
tools are ise9.2

mine is ISEwebpack 10.1 + sp3. I can't downgrade tools suite. ISE9.2
success during PAR but not ISE10.1 (can't place bufgmuxes) see link in
leon_sparc discussion for more...

and in addition to that, there are ddr2 memory access failures, but it
is an other question

On Dec 17, 2:59=A0pm, "Symon" <symon_bre...@hotmail.com> wrote:
> Raph,
>
> Yes it is. You're using too many clocks. If you insist on using all these
> clocks, you are on the way to destruction. (BTW, I spent 2 seconds
> googling - how to do fpga clocking - and found an apparently decent artic=
le
> explaining why this is true. You did google for an answer, right? Maybe n=
ot,
hemes.html)
>
> Whatever, I suggest you RTM.http://www.xilinx.com/support/documentation/u=
ser_guides/ug331.pdf
> Try the section "Quadrant Clock Routing", like you were told to do in the
> original error message.
> Finally, if you post again, tell us specifically for what you're using ea=
ch
> of all these clocks, and ask questions about what you don't understand in
> the user guide linked above.
> Good luck, Symon.
>
> raph wrote:
> > thanks for your replies but it is not that...
> > if you are interested see :
>
> >http://tech.groups.yahoo.com/group/leon_sparc/message/14447
>
> > On Dec 15, 3:55 pm, Gael Paul <gael.p...@gmail.com> wrote:
> >> Hi Raph,
>
> >> I suggest checking your Leon3 configuration. It is likely that you
> >> have a ASIC configuration with clock-gating. When targeting an FPGA,
> >> I believe you should get a single clock per core.
>
> >> - gael
>
>


 0

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