Hi,

I have write simple lockup table:

#################### [CODE] ####################

din  : in  std_logic_vector (3 downto 0);
dout : out std_logic_vector (1 downto 0)

begin

    process(din)
        begin
            case(din) is
                when "000" => dout <= conv_std_logic_vector(2, 2);
                when "001" => dout <= conv_std_logic_vector(0, 2);
                when "010" => dout <= conv_std_logic_vector(1, 2);
                when "011" => dout <= conv_std_logic_vector(1, 2);
                when "100" => dout <= conv_std_logic_vector(2, 2);
                when "101" => dout <= conv_std_logic_vector(3, 2);
                when "110" => dout <= conv_std_logic_vector(3, 2);
                when "111" => dout <= conv_std_logic_vector(0, 2);
               when others => null;
           end case;
    end process;

#################### [/CODE] ####################

But I want to write values in HEX format example:

#################### [CODE] ####################

din  : in  std_logic_vector (3 downto 0);
dout : out std_logic_vector (1 downto 0)

begin

    process(din)
        begin
            case(din) is
                when x"0" => dout <= x"2";
                when x"1" => dout <= x"0";
                when x"2" => dout <= x"1";
                when x"3" => dout <= x"1";
                when x"4" => dout <= x"2";
                when x"5" => dout <= x"3";
                when x"6" => dout <= x"3";
                when x"7" => dout <= x"0";
               when others => null;
           end case;
    end process;

#################### [/CODE] ####################

But with this format i obtain an error ...

"String literal "0000" is of size 4 but is expected to be of size 3."

VHDl x"--" generate bit_vector, but how limit number of bit ?

Thanks.

secureasm

On Apr 7, 9:56=A0am, Kappa <secure...@gmail.com> wrote:
>
> #################### [/CODE] ####################
>
> But with this format i obtain an error ...
>
> "String literal "0000" is of size 4 but is expected to be of size 3."
>
> VHDl x"--" generate bit_vector, but how limit number of bit ?
>
> Thanks.
>
> secureasm

Two choices from my perspective: use Octal instead of heX (O"6")
introduced in VHDL-1993 or extend the case value din to 4 bits with
concatenation.

The one url I grabbed for the VHDL-1993 reference (http://
www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/)
mentions:

"One limitation in VHDL-1993 is that hexadecimal bit-string literals
always contain a multiple of 4 bits, and octal ones a multiple of 3
bits. You can=92t have a 10-bit hexadecimal bit-string literal, or one
containing values other than 0, 1 or _, for example."

On Apr 7, 10:55=A0am, John_H <newsgr...@johnhandwork.com> wrote:
> On Apr 7, 9:56=A0am, Kappa <secure...@gmail.com> wrote:
>
>
>
> > #################### [/CODE] ####################
>
> > But with this format i obtain an error ...
>
> > "String literal "0000" is of size 4 but is expected to be of size 3."
>
> > VHDl x"--" generate bit_vector, but how limit number of bit ?
>
> > Thanks.
>
> > secureasm
>
> Two choices from my perspective: use Octal instead of heX (O"6")
> introduced in VHDL-1993 or extend the case value din to 4 bits with
> concatenation.
>
> The one url I grabbed for the VHDL-1993 reference (http://www.doulos.com/=
knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/)
> mentions:
>
> "One limitation in VHDL-1993 is that hexadecimal bit-string literals
> always contain a multiple of 4 bits, and octal ones a multiple of 3
> bits. You can=92t have a 10-bit hexadecimal bit-string literal, or one
> containing values other than 0, 1 or _, for example."

The error message strangely does not match the declared size of
din as (3 downto 0).  I would have expected the original code to
have an error message...

Hi

> Two choices from my perspective: use Octal instead of heX (O"6")
> introduced in VHDL-1993 or extend the case value din to 4 bits with
> concatenation.

OK for 3 bits I use O"6"  instead of X, but with 5 bits ?

> "One limitation in VHDL-1993 is that hexadecimal bit-string literals
> always contain a multiple of 4 bits, and octal ones a multiple of 3
> bits. You can=92t have a 10-bit hexadecimal bit-string literal, or one
> containing values other than 0, 1 or _, for example."

If I can't have 10 bits then not even 5 bits ?

Thanks.

secureasm

On Apr 7, 11:57=A0am, Kappa <secure...@gmail.com> wrote:
> Hi
>
> > Two choices from my perspective: use Octal instead of heX (O"6")
> > introduced in VHDL-1993 or extend the case value din to 4 bits with
> > concatenation.
>
> OK for 3 bits I use O"6" =A0instead of X, but with 5 bits ?
>
> > "One limitation in VHDL-1993 is that hexadecimal bit-string literals
> > always contain a multiple of 4 bits, and octal ones a multiple of 3
> > bits. You can=92t have a 10-bit hexadecimal bit-string literal, or one
> > containing values other than 0, 1 or _, for example."
>
> If I can't have 10 bits then not even 5 bits ?
>
> Thanks.
>
> secureasm

Maybe you'd do better with VHDL-2008?

Perhaps you could take the suggestion of concatenating your case
variable to get a multiple of 4 bits so it evens out with the compare.

On Wed, 7 Apr 2010 06:56:35 -0700 (PDT), Kappa wrote:

>#################### [CODE] ####################
>
>din  : in  std_logic_vector (3 downto 0);
>dout : out std_logic_vector (1 downto 0)
>
>begin
>
>    process(din)
>        begin
>            case(din) is
>                when "000" => dout <= conv_std_logic_vector(2, 2);
>                when "001" => dout <= conv_std_logic_vector(0, 2);
[...]
>               when others => null;
>           end case;
>    end process;
>
>#################### [/CODE] ####################

YUCK.

You're fighting against VHDL's strict rules, instead of getting 
them to work for you.

Do you like this version better?

  constant  input_bit_width: positive := din'length;
  constant output_bit_width: positive := dout'length;
  subtype T_input_code is integer range 0 to (2**input_bit_width-1);
  subtype T_output_code is integer range 0 to (2**output_bit_width-1);
  type T_code_map is array(T_input_code) of T_output_code;

  ----------------- HERE IS THE LOOKUP TABLE ---------
  constant code_map: T_code_map := (
    0 => 2,
    1 => 0,
    2 => 1,
    3 => 1,
    4 => 2,
    5 => 3,
    6 => 3,
    7 => 0);
  ------------------------------------------------------
  -- You will get errors if you don't provide the full set
  -- of map values, but you can use OTHERS if you wish.
  ...
  process (din) 
    variable code_in: T_input_code;
    variable code_out: T_output_code;
  begin
    code_in := to_integer(unsigned(din));
    code_out := code_map(code_in);
    dout <= std_logic_vector(to_unsigned(code_out, output_bit_width));
  end process;

There are lots of other possibilities; the precise way you choose to
parameterize this design, and set up the constants, depends on how it
fits into the rest of your design and how it will be used.  If you 
are careful and lucky, you can probably avoid the type conversions
in this part of the code, because you are using appropriate numeric
data types in the body of your design.  But that's another discussion.

If you absolutely insist on hex representation, you can easily 
rewrite the map table:

  constant code_map: T_code_map := (
    16#0# => 16#2#,
    ...
    16#7# => 16#0#);

Oh, and I've used numeric_std instead of std_logic_horrible
for the numeric conversions.

Named types, subtypes and constants are your friend, especially
when revisiting the code later, if you choose the names wisely.

I'll leave it to someone else to open a discussion about
the incomplete case statement.
-- 
Jonathan Bromley

Hi,

> You're fighting against VHDL's strict rules, instead of getting
> them to work for you.

I ask those who know more than me ...

> Do you like this version better?
>
> =A0 constant =A0input_bit_width: positive :=3D din'length;
> =A0 constant output_bit_width: positive :=3D dout'length;
> =A0 subtype T_input_code is integer range 0 to (2**input_bit_width-1);
> =A0 subtype T_output_code is integer range 0 to (2**output_bit_width-1);
> =A0 type T_code_map is array(T_input_code) of T_output_code;
>
> =A0 ----------------- HERE IS THE LOOKUP TABLE ---------
> =A0 constant code_map: T_code_map :=3D (
> =A0 =A0 0 =3D> 2,
> =A0 =A0 1 =3D> 0,
> =A0 =A0 2 =3D> 1,
> =A0 =A0 3 =3D> 1,
> =A0 =A0 4 =3D> 2,
> =A0 =A0 5 =3D> 3,
> =A0 =A0 6 =3D> 3,
> =A0 =A0 7 =3D> 0);

How use HEX value ... my request came from them do not want to return
to decimal format ... :-| ...

> =A0 ------------------------------------------------------
> =A0 -- You will get errors if you don't provide the full set
> =A0 -- of map values, but you can use OTHERS if you wish.
> =A0 ...
> =A0 process (din)
> =A0 =A0 variable code_in: T_input_code;
> =A0 =A0 variable code_out: T_output_code;
> =A0 begin
> =A0 =A0 code_in :=3D to_integer(unsigned(din));
> =A0 =A0 code_out :=3D code_map(code_in);
> =A0 =A0 dout <=3D std_logic_vector(to_unsigned(code_out, output_bit_width=
));
> =A0 end process;

Is somewhat more complicated for me but certainly more
professional ...

> There are lots of other possibilities; the precise way you choose to
> parameterize this design, and set up the constants, depends on how it
> fits into the rest of your design and how it will be used. =A0If you
> are careful and lucky, you can probably avoid the type conversions
> in this part of the code, because you are using appropriate numeric
> data types in the body of your design. =A0But that's another discussion.

This is our main problem, avoid conversion of format, I'm translating
a simple C code in VHDL using HEX, I wanted to keep reading two code.

> If you absolutely insist on hex representation, you can easily
> rewrite the map table:
>
> =A0 constant code_map: T_code_map :=3D (
> =A0 =A0 16#0# =3D> 16#2#,
> =A0 =A0 ...
> =A0 =A0 16#7# =3D> 16#0#);

Is perfect ...

> Oh, and I've used numeric_std instead of std_logic_horrible
> for the numeric conversions.
>
> Named types, subtypes and constants are your friend, especially
> when revisiting the code later, if you choose the names wisely.

You are quite right, especially if you often revises the code.

> I'll leave it to someone else to open a discussion about
> the incomplete case statement.

Thanks.

secureasm