I'm working on the high frequency project where I have adc converter 
able to scan Analog signal much faster then fpga.
Is is possible to send a reference clock to ADC, then divide it (by 4 
for example), and the resulting clock move in phase ( intentionally 
skew) into 4 phase shifted clocks.
The simple parallel logic to multiply subtract.

Is it possible at all?

Does anyone has seen such solution in other projects?

Thanks
Robert Dorosa

rosaldorosa pisze:
> I'm working on the high frequency project where I have adc converter 
> able to scan Analog signal much faster then fpga.
> Is is possible to send a reference clock to ADC, then divide it (by 4 
> for example), and the resulting clock move in phase ( intentionally 
> skew) into 4 phase shifted clocks.
> The simple parallel logic to multiply subtract.
> 
> Is it possible at all?
> 
> Does anyone has seen such solution in other projects?
> 
> Thanks
> Robert Dorosa
I have ment divide by 4 into four parallel clock sources shifted in 
phase ( 360deg/4).
Then four parallel aqusition processes.
Then combiner which collects all parallel data together ( compress).

I think it's more clear now.
Regards
Robert Dorosa