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Compiling a design in Quartus that doesn't fit
I want to be able to generate an encrypted netlist of a core using
Quartus. Does Quartus have a switch that allows you to compile a design
that doesn't fit into an FPGA? The issue is that the ports on the core
exceed the number of pins on any device.
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 schvantzkoph (1875)
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3/11/2010 3:05:01 PM |
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"General Schvantzkoph" <schvantzkoph@yahoo.com> wrote in message
news:7vsf4tFaprU4@mid.individual.net...
>I want to be able to generate an encrypted netlist of a core using
> Quartus. Does Quartus have a switch that allows you to compile a design
> that doesn't fit into an FPGA? The issue is that the ports on the core
> exceed the number of pins on any device.
There are settings to allow you to compile lower level entites for incremental
compilation, although I can't remember what they are.
A quick search shows that 'virtual pin' might be what you're looking for, or lead
in the right direction.
Nial.
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 Nial
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3/11/2010 3:25:58 PM
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On Thu, 11 Mar 2010 15:25:58 +0000, Nial Stewart wrote:
> "General Schvantzkoph" <schvantzkoph@yahoo.com> wrote in message
> news:7vsf4tFaprU4@mid.individual.net...
>>I want to be able to generate an encrypted netlist of a core using
>> Quartus. Does Quartus have a switch that allows you to compile a design
>> that doesn't fit into an FPGA? The issue is that the ports on the core
>> exceed the number of pins on any device.
>
>
> There are settings to allow you to compile lower level entites for
> incremental compilation, although I can't remember what they are.
>
> A quick search shows that 'virtual pin' might be what you're looking
> for, or lead in the right direction.
>
>
> Nial.
Thanks, that sounds like what I want.
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General
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3/11/2010 4:23:27 PM
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