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configuration for a mixed mode VHDL-verilog lang

Hi all

My problem is I'd like to choose a VHDL file instantiated inside
verilog via VHDL
configuration

To summerize: I have a hierarcy: "top:vhdl - verilog - Verlog -vhdl:
bottom" How to write a vhdl configuration to select the file for the
bottom instantiation?

Rakesh YC
0
rakesh_yc (1)
7/9/2004 8:05:18 AM
comp.arch.fpga 18587 articles. 2 followers. Post Follow

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guhaoqi
7/9/2004 10:16:56 AM
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