changing DDR2 pin LOC on UCF generated by MIG for virtex4
Am I allowed to change the pin location on the same bank generated b
MIG for my virtex4 design ? Would it not be a hassle or restricted i
I am forced to use the exact pin location for my DDR2 design ? One o
my Virtex4 eval board has it's own fixed DDR2 pins and I would lik
MIG to follow those pins constraint. Thanks a lot
anyone able to help me please
> Am I allowed to change the pin location on the same bank generated by
> MIG for my virtex4 design ? Would it not be a hassle or restricted if
> I am forced to use the exact pin location for my DDR2 design ? One of
...Virtex4 Output Pins during Configuration
I have a problem with a Virtex4 FPGA, I'm using it to control a
motor ... but during the configuration output pins goes high and the
Is there any way to solve the problem without modifying the hardware?
If not ... are pulldown resistors a possible solution? What I mean
is ... even if I put a pulldown resistor if the pin is pulled high by
the FPGA then the pulldown is not useful.
How is the HSWAP_EN pin connected? This enables/disables the internal
weak pullups while configuring.
If the weak pullup is not enabled, then the pin is tristate whil...Need Recommandation for DDR2 controller virtex4
I am trying a new design that includes DDR2. This design has multiple
accses to the memory and I need to use bank interleaving and
auto-precharge function (only on the last access to the read line ,as
expected). CAN someone reccomand me a decent controller that does so
(even if i need to buy it)? I have tried xilinx MIG but it doesn't
Try Northwest Logic--they do good work but you have to pay for it.
On Sun, 24 Dec 2006 03:46:05 -0800, Guy_FPGA wrote:
> Hello all,
> I am trying a new design t...Altera Cyclone II DQ/DQS pins location
I have an issue with porting my high-speed DDR interface to Altera
Cyclone II device. As far as datasheet says, Altera Cyclone II device
does not have any dedicated circuitry to support DDR signaling in its
Input/Output blocks for DQ pins. The only thing present in hardware is
the clock delay circuitry on DQS pins. All other DDR logic is
implemented using LUT's and triggers from adjacent Logic Array
Blocks. So, it seams that we have only DQS pins location fixed,
whenever all other DDR pins may float within the selected IO bank. Is
that right? If yes, then what is the reason t...DDR2: Why do I see two edges of a 125MHz DQS on the IDELAY
I'm working on a Virtex4 DDR2 interface based on the direct clocking
design from MIG 1.6 (XAPP701). I'm clocking the DDR2 (Micron 1Gb) at
125MHz, so I would expect to see only one edge of DQS during
calibration using the IDELAY. However, from chipscope I see two edges
only approx 900ps apart.
I notice there are lots of IDELAY queries on here... can anyone
explain what is going on?
The design uses an IDELAYCTRL clocked at 200MHz from a DCM CLKFX with
a 50MHz clkin.
The result is intermittant read errors, I suspect since the calibrated
data delay is totally wrong...
Many thanks,...Virtex4: On using a LC clock pin for global clock.
Can one use a CC_LC (regional clock) to drive the global clock tree via a BUFG or IBUFG primitive?
I assume this is a bad design practice, because CC_LC are 'external' pins, whereas GC pins are located near the center of the die...
Do I risk a high clock skew resulting in poor synthesized frequency?
> Can one use a CC_LC (regional clock) to drive the global clock tree
via a BUFG or IBUFG primitive?
> I assume this is a bad design practice, because CC_LC are 'external'
pins, whereas GC pins are located near the center of the die...
>...[Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
I'm using a V4SX55-FF1148 device and as framebuffer i have build a DDR2
controller ... now i'm having 2 of those controllers in the same device
and controller 1 is working perfectly but in controller 0 i have 2 pins
that always read 1. no matter what. those 2 pins happen to be on a dual
purpose pin (D0/D1 from configuration, but i'm using the serial slave
All the VREF's are connected to the device on +0.9V, all the
IDELAYCTRL's are correctly locked since the other pins of the
framebuffer on the same bank give no issue and are working fine ...
this is ...Schematic pin to pin tracer
Given a starting pin, starting cell name & ending cellname(All in the
same hierarchy), to find the mapping between the starting pin and the
actual pin it is connected to in the ending cell name(stop level).
Looks to me like a big graph theory problem, open to ideas about
But since Cadence already has leHiProbe, am tempted to check and see if
they have any canned skill function?
What I can think off:
Start out "waves" from the starting pin:cellName and stop when you hit
on the endingcell name, and grab the pinname of that instance
Not very cl...fpga pin to pin conecting
Can someone please help me. If I have to connect two FPGA circuits on
the same board and their pins are not compatible waht should I do?
If someone knows some good link about this, anything that you think
that will be useful, please tell me.
On Jan 14, 7:48=A0am, Zorjak <Zor...@gmail.com> wrote:
> Hi everyone
> Can someone please help me. If I have to connect two FPGA circuits on
> the same board and their pins are not compatible waht should I do?
> If someone knows some good link about this, anything that you think
> that will be useful, p...DQS
whats the matter with DQS? Is it maintaned still? Where to get it?
The link to
ftp.fsu.edu -> dead
ftp.scri.fsu.edu -> dead
ftp.psc.edu -> sime limited code
...re-attach pin text to pin
Is there a way to re-attach the text its pin so it moves when the pin
> Is there a way to re-attach the text its pin so it moves when the pin
> is moved?
There is an "Attach" function, somewhere down in the menus.
Right now don't have time to look for it, but I know it's there.
...80 Pin to 68 Pin converter
I built a new computer (for home use) and I wanted really fast drives
so I bought 15K RPM Ultra 320 SCSI drives
Hitachi Ultrastar HUS153014VL3800 and FUJITSU Enterprise MAU3073NC and
I bought a Adaptec SCSI Card 39320D. I didnt realize at the time that
the drives were 80 pin.
So I couldnt use them at the time I got together the rest of my parts
so I just threw in a IDE drive till I get this all sorted out and I
need some advise.
So I understand I need a 80 pin to 68 pin converter to make these
drives usefull to me I guess. From what I have researched so far I
found that I cant find...68 Pin Versus 80 Pin
Is there a difference between a 68 pin and an 80 pin cable? Is one better
I am getting ready to buy a drive and have an opportunutity to get a Maxtor
15k drive. One has a 68 pin connector and one has an 80 pin. I want the
better or faster of the two. I know nothing of SCSI and presently don't have
any SCSI devices in my computer. I will run a single SCSI drive now and may
use a raid setup at a later date but I'm not sure. I fooled with SCSI a few
years back (SCSI CD writer). Never could get it to work. Hopefully this
experience will fare better.
Also, does anyone have a s...80 Pin to 68 Pin adapters
I have acquired an Adaptec host SCSI card 2940UW with a 68 pin
internal connector. This came with four Quantum QM318200TD SCSI hard
drives with 80 pin connectors but only one 80-68 adapter. OK I can use
the drives one at a time, great fun, but can anyone point me to the
best one of these possible choices please:
1) Is there such a thing as an 80-68 adapter that fits on the Adaptec
card, so I can use an 80-pin cable from all four drives leading to the
single 80-68 adapter on the Adaptec card? The lack of power pins on
the HDD's does raise an obstacle there!
2) My initial research tells me ...Digital pin used as analog pin
i want use a digital pin as analog output voltage: is it possible
linear decrease voltage (maybe with a proper 1-0 combination) as
output without PWM?
On Oct 12, 12:18 pm, fasf <silusilus...@gmail.com> wrote:
> i want use a digital pin as analog output voltage: is it possible
> linear decrease voltage (maybe with a proper 1-0 combination) as
> output without PWM?
You could do PWM in software using a timer interrupt.
> i want use a digital pin as analog output voltage: is it possible
> linear decrease voltage (maybe with a proper 1-0 combinat...Cartridge connector/pin-pin replacements
I'm working on a project where I want to daisy-chain and hard-wire
several cartridge devices, but I'm having trouble locating connectors
that go in the place of the cartridge connectors.
>From what I've heard and can measure (though I'm not 100% sure if it's
correct or just due to misalignment in mounting/soldering in the
device I've been measuring) the Atari ST cartridge connector has two
rows of 20 pins each.
Those two rows are spaced 5mm apart, while the pins are spaced 2mm
apart from each other.
Since my setup will be a permanent one and the cartridg...Motion Control Connector (15 pin) Checking the Dir(CW) Pin#4 and Dir(CCW) pin#12
I want to check the output (digital 5V) from my Control Connector in the UMI-7774 on Axis#1.
The Control Connector (15 pin) has Dir(CW) Pin#4 and Dir(CCW) pin#12
which i need to connect to my Servo motor drive (Forward and Reverse inputs in the Motor Drive, Both 24VDC).
I connect these pins : Dir(CW) Pin#4 and Dir(CCW) pin#12 to the Forward and Reverse inputs in the Motor Drive,
I use a 24vdc relay with 5v coil (of the relay), and as i test it in Motion Assistant the Servo motor NOT MOVE !
So, i wanted to test if the Dir(CW)&...24 pin
Where does one buy a 24pin to 28pin Eprom kernal adapter, with a
toggle switch for two different kernals, just like a JD ??
I thought I had heard people where buying a bunch of PCB boards and
making them. Are they
doing this for self or for resell ??
You can get one here from Ebay
On Oct 29, 3:00=A0pm, bluebirdpod <bluebird...@gmail.com> wrote:
> Where does one buy a 24pin to 28pin Eprom kernal adapter, with a
> toggle switch for two different kernals, just like a JD ??
> I thought I...68 pin to 80 Pin SCA Adapter
Anyone know the correct setup to use an 68 pin to 80 Pin SCA Adapter?
Here's a link to an image of the adapter I'm trying to use:
I am trying to use this to connect an 80 Pin SCA HD to my MegaRAID 1600
elite U160 controller. I currently have it setup on a 4 position
terminated cable: position 1 is my Adapter, position 2 is empty,
position 3 is my HD (with adapter & power), position for is my LVD/SE
The HD is setup for SCSI ID 3 (on the adapter). There are jumper
options for LED, SYN, DLY, MTR also on the adapter.
...When do you pin out?
Hey y'all --
Lately my company's been poking around at our overall design flow,
trying to work out how to make things happen in better, more logical
fashions. And one of the things that comes to mind is the pinning of
FPGAs, i.e. determining which signal's going to go where.
Traditionally around here, we've allowed the pinning to be pretty much
at the PCB layout engineer's discretion with only minimal input from
me, i.e. this has to go to a GCLK, these all need to be on the same I/O
bank for voltage reasons.
I was just wondering how everyone else fits actuall...Need 40 pin Machine PIN Socket...
Hey everyone!! I am doing a hardware project on my CDTV and I need to
get a 40 pin Machine pin (round hole) socket. Does anyone here have one
they could sell me or know where I can buy one? Radio Shack only
carries the cheap dual wipe sockets and this won't work for my purpose.
Thanks in advance!!
P.S. Please respond here in newsgroup!
Macintosh Dragon wrote:
> Hey everyone!! I am doing a hardware project on my CDTV and I need to
> get a 40 pin Machine pin (round hole) socket. Does anyone here have one
> they could sell me or know where I can buy one? R...50-pin device on 68-pin bus?
Am I right in assuming that I cannot use a 50-68 adapter to connect a
50-pin drive to a 68-pin SCSI card --even if it's the only device on
that bus? There would be a bunch of unterminated lines, right?
Percival P. Cassidy <email@example.com> wrote:
> Am I right in assuming that I cannot use a 50-68 adapter to connect a
> 50-pin drive to a 68-pin SCSI card --even if it's the only device on
> that bus? There would be a bunch of unterminated lines, right?
as long as the 68 pin cable is terminated you can.
the below is ok.
controller 68 pin...Unused Pin setting on per-pin basis
I've got a custom FPGA board with a number of peripherals connected to
the FPGA. I need to keep the connections between the FPGA and unused
peripherals in a sensible state.
Is there a way I can define FPGA pins as inputs with different
pull-up/pull-down/floating states without including dummy signals in my HDL.
bitgen offers the option to set ALL unused pins to
pull-up/pull-down/floating, but I need to set this on a per/pin basis.
Any ideas anyone?
On 2 Mai, 10:11, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote:
> Hi all,
> I've got a custom F...25 pin serial to 9 pin serial?
I have an old pen plotter (Houston Instrument DMP-50) which has a 25 pin
serial port. Can I hook this up to a 'modern' 9 pin serial connector? Is
there a connector/adaptor I can use? Or is there some other way to hook
up to the port?
Michael Soibelman wrote:
> I have an old pen plotter (Houston Instrument DMP-50) which has a 25 pin
> serial port. Can I hook this up to a 'modern' 9 pin serial connector? Is
> there a connector/adaptor I can use?
Yes and yes. Check any cable supplier. They should have 9-25 adapters.
Michael Soibelman wrote:
> I h...