fpga pin to pin conecting
Can someone please help me. If I have to connect two FPGA circuits on
the same board and their pins are not compatible waht should I do?
If someone knows some good link about this, anything that you think
that will be useful, please tell me.
On Jan 14, 7:48=A0am, Zorjak <Zor...@gmail.com> wrote:
> Hi everyone
> Can someone please help me. If I have to connect two FPGA circuits on
> the same board and their pins are not compatible waht should I do?
> If someone knows some good link about this, anything that you think
> that will be useful, p...changing DDR2 pin LOC on UCF generated by MIG for virtex4
Am I allowed to change the pin location on the same bank generated b
MIG for my virtex4 design ? Would it not be a hassle or restricted i
I am forced to use the exact pin location for my DDR2 design ? One o
my Virtex4 eval board has it's own fixed DDR2 pins and I would lik
MIG to follow those pins constraint. Thanks a lot
anyone able to help me please
> Am I allowed to change the pin location on the same bank generated by
> MIG for my virtex4 design ? Would it not be a hassle or restricted if
> I am forced to use the exact pin location for my DDR2 design ? One of
...Pin Locking on a FPGA
A quick question for the group:
With the flexibility of today's FPGAs, is it still better to do the
VHDL or Verlog design through Synthesis and then lock pins on the FPGA
or could pins be locked on the FPGA before the design is synthesized?
I looking for the quickest way to get to a PCB. My design has various
buses. One of the buses is PCI.
> With the flexibility of today's FPGAs, is it still better to do the
> VHDL or Verlog design through Synthesis and then lock pins on the FPGA
> or could pins be locked on the FPGA before t...fpga- DDR or DDR2
I would need to begin a new fpga design intefacing with external SODIMM
at a rate of 400 Mbit/sec/pin.
I have 2 alternatives DDR-SODIMM and DDR2-SODIMM.
>From fpga interface prespective, which of them is advantagious ?
Try to find out if the different FPGA manufacturers offer embedded
which will make your life easier when trying to implement DDR/DDR2.
Of course there are also IP cores provided by the manufacturers.
Contact some FAEs.
If you want to implement DDR on your own "from scratch" it will be a
job in my opinion.
...rules to assign pins to FPGA?
I am a newbie and I need rules to assign pins to FPGA. I would imagine some,
1. Group signals that are natually related, and assign them to the same I/O
bank/side of the FPGA;
2. Let the software to assign pins, then fix some pins according to the
automatic assignment, then let the software run again. Do this iteratively
for several times.
What is your experience? Suggestions are welcomed.
My recent experience is with Altera Cyclone
I needed to lay out the PCB first, so this is how I did it :
1 - Best possible layout for power supply pins and decouplers
2 - Best layout f...DDR2 FPGA PWB SIMULATION
We are doing a design that uses an Altera Cyclone II to drive three DDR2
memory chips. Looking at
reference designs from Altera, TI and another company the terminations run
the spectrum from
series parallel (Altera), just series (TI) to no resistor termination (the
So my questions are to those designers who have DDR2 interface experience
1. What kind of terminations did you use?
2. Did you model the PWB and simulate for signal integrity?
3. If you did sim the PWB how close did the simulation results agree with
the results from physical PWB?
4. What simulat...Virtex4 FPGA minimum power
A Virtex4 FPGA is mounted on a board which has a sleep mode to conserve
battery power during periods of inactivity. Is it only necessary to
keep the VCCaux power on to maintain the configuration memory, and all
the other power inputs can be turned off?
The Vcc_config must stay powered, the Vcc_aux must stay powered, and the
Vccint must stay powered.
If any of these drops below their power on reset thresholds, the device
erases all memory before trying to configure.
Vcco_config POR trip is ~ 0.5 to 0.75V
Vcc_aux POR trip is ~1.3 to 1.8V
Vccint POR trip is ~0.5 to 0.75V
I recomm...FPGA pin re-configuration
Our existing Xilinx FPGA board has some test output pins of type
IO_LXXY_#. They are now configured as IOSTANDARD = LVDS_25 and
IOSTANDARD = LVTTL. They are connected to TSW connectors.
We wanted to configure them as input pins. Is there anything that we
should pay attention on?
Where can I find the information on how to design the input and output
buffers on PCB? Thanks in advance!
>Our existing Xilinx FPGA board has some test output pins of type
>IO_LXXY_#. They are now configured as IOSTANDARD = LVDS_25 and
>IOSTANDARD = LVTTL. They are connected to TSW connectors.
>We wanted ...how to import fpga pin groups?
When you import a pin assignment file in Quartus, pin group names are
Quartus assignes its own group names.
Does anyone know how to avoid this?
I have the following line in the assignment file,
the group name is DEMOD
This does not appear in the pin assignment editor.
> When you import a pin assignment file in Quartus, pin group names are
> not read.
If I say Assignment, Pins, I get a table with column headings.
If I say File, Export, CVS from there I g...FPGA to FPGA Bus
I would like to connect 3 FPGA devices together using a 32-bit bus. Also
would like all 3 to be masters on the bus. Is there any standard bus ou
there that would do this rather than me coming up with my own idea.
On Oct 16, 2:48 pm, "maxascent" <maxasc...@yahoo.co.uk> wrote:
> I would like to connect 3 FPGA devices together using a 32-bit bus. Also I
> would like all 3 to be masters on the bus. Is there any standard bus out
> there that would do this rather than me coming up with my own idea.
Search for hypertunnel (HT) chip-to-...Virtex4 Output Pins during Configuration
I have a problem with a Virtex4 FPGA, I'm using it to control a
motor ... but during the configuration output pins goes high and the
Is there any way to solve the problem without modifying the hardware?
If not ... are pulldown resistors a possible solution? What I mean
is ... even if I put a pulldown resistor if the pin is pulled high by
the FPGA then the pulldown is not useful.
How is the HSWAP_EN pin connected? This enables/disables the internal
weak pullups while configuring.
If the weak pullup is not enabled, then the pin is tristate whil...FPGA pin swapping utility
We are using V5LX110T and V5L330 FPGAs. Are there decent pin swapping
utilities so that we do not have to spend a lot of time in PCB Laout
to do the pin swapping? I am hoping that the tool shows the BGA view
of the FPGA and lets the user to swap pins such that there is good
break out from the FPGA.
> We are using V5LX110T and V5L330 FPGAs. Are there decent pin swapping
> utilities so that we do not have to spend a lot of time in PCB Laout
> to do the pin swapping? I am hoping that the tool shows the BGA view
> of the FPGA and lets the use...Assign FPGA pins to submodule
I'm currently working with ISE 7.1
I'd like to be able to assign FPGA pins to a submodule either via a ucf
file, or (preferably) via assigning properties to nets within the
To expand-- I'm creating some modules for use as library blocks in a
classroom setting. These blocks will always be mapped to static FPGA
pins, corresponding to LEDs, pushbuttons, etc, so I'd like to be able
to just drag and drop them onto a schematic, without having to create
top level I/O markers.
I know this was possible in ISE 2.1 (the version the class is currently
using), but is it still pos...inout pins use in fpga
I am using "inout" signal for the first time in designing I2C
communication with cmos sensor module.I have completed the design. The
post map simulation worked fine and synthesized without warnings and
errors. But when I implemented the design in Spartan 3A DSP by using
pull up resistors for the pins I couldnot get the output.Suggest me
about using the "inout" pins.
denish <firstname.lastname@example.org> wrote:
> I am using "inout" signal for the first time in designing I2C
> communication with cmos sensor module.I have completed th...