DDR2 dqs pin // virtex4

Hi,

I just bougth a card with FPGA "Virtex4 XC4VLX60 668pinBGA -11"
The board is equiped with a DDR2 SDRAM memorie.
FPGA and memory is connected with signals such as DQ[0:15], DQS[0:1],
DQSN[0:1].
I use Xilinx controler (MIG 1.72) in ISE 9.1.03i.

The pinout of this board is :
DDR2_DQS0 => PIN number M21 (IO_L13P_9)
DDR2_DQS0_N => PIN number M2O (IO_L13N_9)
DDR2_DQS1 => PIN number K20 (IO_L5N_9)
DDR2_DQS1_N => PIN number L19 (IO_L5P_9)

I have an error in ISE, because there is an inversion between DQS1 <->
DQS1_N
DDR2_DQS1 should have PIN number L19 (IO_L5P_9)
(When I do this inversion in ucf file, I can route my FPGA)

Please, see below the VHDL code (MIG 1.72).

Can you help me to find a solution to modify the VHDL code, and so get round
the bug pinout of this board
Thanks lot.

Regards,
Benoit.

The VHDL code (MIG 1.72) is :
----------------------------------------------------------------------------
---
-- Device      : Virtex-4
-- Design Name : DDR2 Direct Clocking
-- Purpose     : This module places the data stobes in the IOBs.
----------------------------------------------------------------------------
---

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity mem_interface_top_v4_dqs_iob is
  port (
    CLK          : in    std_logic;
    RESET        : in    std_logic;

    DLYINC       : in    std_logic;
    DLYCE        : in    std_logic;
    DLYRST       : in    std_logic;
    CTRL_DQS_RST : in    std_logic;
    CTRL_DQS_EN  : in    std_logic;
    DDR_DQS      : inout std_logic;
    DDR_DQS_L    : inout std_logic;
    DQS_RISE     : out   std_logic
    );
end entity;

architecture arc_v4_dqs_iob of mem_interface_top_v4_dqs_iob is

  signal dqs_in         : std_logic;
  signal dqs_out        : std_logic;
  signal dqs_delayed    : std_logic;
  signal ctrl_dqs_en_r1 : std_logic;
  signal vcc            : std_logic;
  signal gnd            : std_logic;
  signal clk180         : std_logic;
  signal data1          : std_logic;
  signal DQS_UNUSED     : std_logic;

  signal RESET_r1       : std_logic;

begin

  vcc    <= '1';
  gnd    <= '0';
  clk180 <= not CLK;

  process(CLK)
  begin
    if (CLK = '1' and CLK'event) then
      RESET_r1 <= RESET;
    end if;
  end process;

  process(clk180)
  begin
    if clk180'event and clk180 = '1' then
      if (CTRL_DQS_RST = '1') then
        data1 <= '0';
      else
        data1 <= '1';
      end if;
    end if;
  end process;

  idelay_dqs : IDELAY
    generic map(
      IOBDELAY_TYPE  => "VARIABLE",
      IOBDELAY_VALUE => 0
      )
    port map (
      O   => dqs_delayed,
      I   => dqs_in,
      C   => CLK,
      CE  => DLYCE,
      INC => DLYINC,
      RST => DLYRST
      );

  iddr_dqs : IDDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
      SRTYPE       => "SYNC"
      )
    port map (
      Q1 => DQS_RISE,
      Q2 => DQS_UNUSED,
      C  => CLK,
      CE => vcc,
      D  => dqs_delayed,
      R  => RESET_r1,
      S  => gnd
      );

  oddr_dqs : ODDR
    generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      SRTYPE       => "SYNC"
      )
    port map (
      Q  => dqs_out,
      C  => clk180,
      CE => vcc,
      D1 => data1,
      D2 => gnd,
      R  => gnd,
      S  => gnd
      );

  tri_state_dqs : FD
    port map (
      D => CTRL_DQS_EN,
      Q => ctrl_dqs_en_r1,
      C => clk180
      );


  iobuf_dqs : IOBUFDS
    port map (
      O   => dqs_in,
      IO  => DDR_DQS,
      IOB => DDR_DQS_L,
      I   => dqs_out,
      T   => ctrl_dqs_en_r1
      );



end arc_v4_dqs_iob;


0
bhb22l (2)
11/22/2007 9:33:25 AM
comp.arch.fpga 18483 articles. 2 followers. Post Follow

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bhb wrote:
> Hi,
> 
> I just bougth a card with FPGA "Virtex4 XC4VLX60 668pinBGA -11"
> The board is equiped with a DDR2 SDRAM memorie.
> FPGA and memory is connected with signals such as DQ[0:15], DQS[0:1],
> DQSN[0:1].
> I use Xilinx controler (MIG 1.72) in ISE 9.1.03i.
> 
> The pinout of this board is :
> DDR2_DQS0 => PIN number M21 (IO_L13P_9)
> DDR2_DQS0_N => PIN number M2O (IO_L13N_9)
> DDR2_DQS1 => PIN number K20 (IO_L5N_9)
> DDR2_DQS1_N => PIN number L19 (IO_L5P_9)
> 
> I have an error in ISE, because there is an inversion between DQS1 <->
> DQS1_N
> DDR2_DQS1 should have PIN number L19 (IO_L5P_9)
> (When I do this inversion in ucf file, I can route my FPGA)
> Can you help me to find a solution to modify the VHDL code, and so get round
> the bug pinout of this board

I don't understand - you have an error in the ucf file, you changed the 
ucf file, it fixed the problem but you want a different solution so that 
you don't have the change the ucf file?

Your VHDL code directly instantiates the IOB. ISE 'knows' to which pins 
the IO and IOB outputs of IOBUFDS can connect. Your VHDL connects the 
DQS pins using vector notation, which is good because it is concise and 
understandable. If you wanted to change the VHDL, you could instantiate 
the IOBUFDS of each DQS separately. For the DQS that has the error in 
the ucf, change the signal names to match the ucf. This will make an 
inverted DQS output, so be sure to invert that DQS bit somewhere in the 
DQS generation logic. Check the timing carefully to make sure that the 
inversion doesn't cause any timing errors. Finally, put in a comment 
explaining why you made this change.

I had a similar problem on a design, except that the PC board had an 
error and the N FPGA output went to a P SDRAM input; the P FPGA output 
went to the N SDRAM input. I inverted the signal before the IOB then 
commented it carefully so that months later I wouldn't wonder why that 
signal was coded differently than the rest. (It was my job to check to 
PCB artwork before fab, too.)


---
Joe Samson
Pixel Velocity
0
Joseph
11/22/2007 3:43:57 PM
Thank you for comment.
I need to change my file.ucf to route the FPGA. So, the information is
opposite.
DQS0 should have the same information as DQS1 (I use Lower and Upper byte in
memory).
But with this chnage in ucf, DQS0 = DQS1_N.

I changed IOBUFDS for only DQS1, DSQ1_N
I invert DQS1 bit in the DQS1 generation logic, but I have no result in the
board (the source code was tested
in a other DDR2 memory with success).

I don't know if the problem is a timing or other.

Could you indicate me an example (please find the code in my first mail) to
invert  DQS1 bit in the DQS1 generation logic.
Thanks lot in advance.

Best regards,
Benoit.

"Joseph Samson" <user@not.my.company> a �crit dans le message news:
1th1j.70646$YL5.24511@newssvr29.news.prodigy.net...
> bhb wrote:
> > Hi,
> >
> > I just bougth a card with FPGA "Virtex4 XC4VLX60 668pinBGA -11"
> > The board is equiped with a DDR2 SDRAM memorie.
> > FPGA and memory is connected with signals such as DQ[0:15], DQS[0:1],
> > DQSN[0:1].
> > I use Xilinx controler (MIG 1.72) in ISE 9.1.03i.
> >
> > The pinout of this board is :
> > DDR2_DQS0 => PIN number M21 (IO_L13P_9)
> > DDR2_DQS0_N => PIN number M2O (IO_L13N_9)
> > DDR2_DQS1 => PIN number K20 (IO_L5N_9)
> > DDR2_DQS1_N => PIN number L19 (IO_L5P_9)
> >
> > I have an error in ISE, because there is an inversion between DQS1 <->
> > DQS1_N
> > DDR2_DQS1 should have PIN number L19 (IO_L5P_9)
> > (When I do this inversion in ucf file, I can route my FPGA)
> > Can you help me to find a solution to modify the VHDL code, and so get
round
> > the bug pinout of this board
>
> I don't understand - you have an error in the ucf file, you changed the
> ucf file, it fixed the problem but you want a different solution so that
> you don't have the change the ucf file?
>
> Your VHDL code directly instantiates the IOB. ISE 'knows' to which pins
> the IO and IOB outputs of IOBUFDS can connect. Your VHDL connects the
> DQS pins using vector notation, which is good because it is concise and
> understandable. If you wanted to change the VHDL, you could instantiate
> the IOBUFDS of each DQS separately. For the DQS that has the error in
> the ucf, change the signal names to match the ucf. This will make an
> inverted DQS output, so be sure to invert that DQS bit somewhere in the
> DQS generation logic. Check the timing carefully to make sure that the
> inversion doesn't cause any timing errors. Finally, put in a comment
> explaining why you made this change.
>
> I had a similar problem on a design, except that the PC board had an
> error and the N FPGA output went to a P SDRAM input; the P FPGA output
> went to the N SDRAM input. I inverted the signal before the IOB then
> commented it carefully so that months later I wouldn't wonder why that
> signal was coded differently than the rest. (It was my job to check to
> PCB artwork before fab, too.)
>
>
> ---
> Joe Samson
> Pixel Velocity


0
bhb
11/22/2007 4:53:42 PM
bhb wrote:
> Thank you for comment.
> I need to change my file.ucf to route the FPGA. So, the information is
> opposite.
I'm sorry that I still don't understand what you're telling me. Can you 
explain why fixing the ucf file isn't the correct solution and can you 
please tell me what the original ISE error was?

> I changed IOBUFDS for only DQS1, DSQ1_N
> I invert DQS1 bit in the DQS1 generation logic, but I have no result in the
> board (the source code was tested
> in a other DDR2 memory with success).

Can you explain this in much more detail? What do you mean that the 
source code was tested in another DDR2 memory with success?

> Could you indicate me an example (please find the code in my first mail) to
> invert  DQS1 bit

My VHDL is rusty, how about:
   iobuf_dqs : IOBUFDS
     port map (
       O   => dqs1_in,
       IO  => DDR_DQS1,
       IOB => DDR_DQS1_L,
       I   => not dqs1_out,
       T   => ctrl_dqs_en_r1
       );

---
Joe
0
Joseph
11/23/2007 12:28:40 AM
Thank Joseph for your comment.

ISE 'knows' to which pins the IO and IOB outputs of IOBUFDS can connect.
I found the solution to not modify my ucf pinout, and not modify the logic
value of  DQS and DQS_N.
I changed the IOBUFDS, and used IOBUF and ODDR. With ISE, I can connect :
DQS_N => PIN  IO_P
DQS => PIN  IO_N

In ucf , use IOSTANDART = SSTL18_II
(not DIFF_SSTL18_DCI).

I routed this solution, and the test is OK on the board.

Benoit.


"Joseph Samson" <user@not.my.company>
a �crit dans le message news:
Y8p1j.19185$4V6.8763@newssvr14.news.prodigy.net...
> bhb wrote:
> > Thank you for comment.
> > I need to change my file.ucf to route the FPGA. So, the information is
> > opposite.
> I'm sorry that I still don't understand what you're telling me. Can you
> explain why fixing the ucf file isn't the correct solution and can you
> please tell me what the original ISE error was?
>
> > I changed IOBUFDS for only DQS1, DSQ1_N
> > I invert DQS1 bit in the DQS1 generation logic, but I have no result in
the
> > board (the source code was tested
> > in a other DDR2 memory with success).
>
> Can you explain this in much more detail? What do you mean that the
> source code was tested in another DDR2 memory with success?
>
> > Could you indicate me an example (please find the code in my first mail)
to
> > invert  DQS1 bit
>
> My VHDL is rusty, how about:
>    iobuf_dqs : IOBUFDS
>      port map (
>        O   => dqs1_in,
>        IO  => DDR_DQS1,
>        IOB => DDR_DQS1_L,
>        I   => not dqs1_out,
>        T   => ctrl_dqs_en_r1
>        );
>
> ---
> Joe


0
bhb
11/27/2007 8:08:13 AM
Reply:

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