EDK custom IP read/write

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Hi,

I'm missing something here, I think. I used EDK create/import IP wizard
to create a custom IP that has one s/w accessible register. I want to
modify the data (shift, rotate, add, etc.) received from a terminal and
read it back. I didn't modify the slave read/write example code
generated. I wrote a program in C that uses custom IP library for
read/write, but I always read a 0. If I hardcode IP2Bus_Data, I could
read that data. I did a test that read/write LEDs before, and it worked
just fine. But it seems like I couldn't get it to work if I just modify
the Bus2IP_Data signal and read it back. I'm not familiar with VHDL.
Can anyone point out to me? Thanks!


Auto generated read/write that I use:
  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
  begin

    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        slv_reg0 <= (others => '0');
      else
        case slv_reg_write_select is
          when "1" =>
            for byte_index in 0 to (C_DWIDTH/8)-1 loop
              if ( Bus2IP_BE(byte_index) = '1' ) then
                slv_reg0(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
              end if;
            end loop;
          when others => null;
        end case;
      end if;
    end if;

  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model register read mux
  SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0 ) is
  begin

    case slv_reg_read_select is
      when "1" => slv_ip2bus_data <= slv_reg0;
      when others => slv_ip2bus_data <= (others => '0');
    end case;

  end process SLAVE_REG_READ_PROC;

  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data        <= slv_ip2bus_data;
  IP2Bus_Ack         <= slv_write_ack or slv_read_ack;
  IP2Bus_Error       <= '0';
  IP2Bus_Retry       <= '0';
  IP2Bus_ToutSup     <= '0';

0
Reply dasani8888 (18) 10/25/2005 7:08:55 PM

Hi again,
I forgot to mention my target is virtex-II pro fpga. Thanks.

0
Reply Eric 10/25/2005 7:31:38 PM


I am wondering the same thing too.  Have you solve your problem?

Regards
HV	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
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0
Reply hvo 12/16/2009 7:49:01 PM

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