I have designed a slave OPB peripheral, simulated with VCS to check for 
the correct functionality and imported it into EDK. All was fine.

In EDK, when generating the netlist, the HDL code is synthesized using 
XST (Xilinx Synthesis Tool), so that the netlist can be generated.

The problem I'm having is that there is an "inout" port in my user logic 
that should go/come all the way up to/from the top level but for some 
reason, when XST generates an HDL wrapper to my user logic, it expects 
my sub-module to have 1 input and 2 output ports (see the error below) 
instead of just the one inout port, as if I had to use directly the 
input/outputs of an IOBUF instead of just one inout, e.g.:

// this is just an example:
IOBUF txrx
             (
              .I ( TXRX_IO_I ), // input
              .IO ( TXRX_IO ),  // inout
              .O ( TXRX_IO_O ), // output
              .T ( TXRX_IO_T )  // ouput enable
             );

In my code I have something like this:

// port declaration
inout TXRX_IO;

assign TXRX_IO = TxEn? 1'bz:0;  // output, pull up assumed

if (CanRead)
    Read_reg <= TXRX_IO; // input

This is a very simple and elegant Verilog code that infers a tristate 
buffer. Surely I should not have to change my design to use the 3 extra 
ports instead of just the one inout.

Also, in my *.mhs file I clearly stated that it should be an external port:
# Global Ports
  PORT TXRX_IO = txrx, DIR = IO # txrx connects to the peripheral's 		 
                              # TXRX_IO port


If you have any clues about how this can be solved, I'll appreciate if 
you could post them in here. Many thanks.

TonyF



XST error message:
------------------------------------------------
Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD 
option IMP_NETLIST=TRUE indicates that a NGC file is to be produced 
using XST synthesis. IMP_NETLIST=FALSE (default) instances are not 
synthesized. A batch file, synthesis.sh, has been created that allows 
you to synthesize those instances in your specified synthesis tool of 
choice.

opb_txrx_0_wrapper (opb_txrx_0) -
C:\EDK_examples\v2pro_eval_mgt2\system.mhs:397 - Running XST synthesis
ERROR:HDLCompilers:91 - ../hdl/opb_txrx_0_wrapper.v line 64 Module 
'opb_txrx' does not have a port named 'TXRX_IO_I'
ERROR:HDLCompilers:91 - ../hdl/opb_txrx_0_wrapper.v line 65 Module 
'opb_txrx' does not have a port named 'TXRX_IO_O'
ERROR:HDLCompilers:91 - ../hdl/opb_txrx_0_wrapper.v line 66 Module 
'opb_txrx' does not have a port named 'TXRX_IO_T'
ERROR:MDT - HDL synthesis failed!

There's details on the use INOUT ports through EDK.

Using the following syntax in the mpd file:
PORT TXRX_IO = "", DIR = INOUT, THREE_STATE = FALSE, IOB_STATE = BUF

This tells platgen not to expand the _I/_O/_T tri-ports.

Read psf_rm.pdf (6.3i) for details.
"Microprocessor Peripheral Definition"->"Design Considerations"->
"Tri-state (InOut) Signals"

TonyF wrote:
> I have designed a slave OPB peripheral, simulated with VCS to check for 
> the correct functionality and imported it into EDK. All was fine.
> 
> In EDK, when generating the netlist, the HDL code is synthesized using 
> XST (Xilinx Synthesis Tool), so that the netlist can be generated.
> 
> The problem I'm having is that there is an "inout" port in my user logic 
> that should go/come all the way up to/from the top level but for some 
> reason, when XST generates an HDL wrapper to my user logic, it expects 
> my sub-module to have 1 input and 2 output ports (see the error below) 
> instead of just the one inout port, as if I had to use directly the 
> input/outputs of an IOBUF instead of just one inout, e.g.:
> 
> // this is just an example:
> IOBUF txrx
>             (
>              .I ( TXRX_IO_I ), // input
>              .IO ( TXRX_IO ),  // inout
>              .O ( TXRX_IO_O ), // output
>              .T ( TXRX_IO_T )  // ouput enable
>             );
> 
> In my code I have something like this:
> 
> // port declaration
> inout TXRX_IO;
> 
> assign TXRX_IO = TxEn? 1'bz:0;  // output, pull up assumed
> 
> if (CanRead)
>    Read_reg <= TXRX_IO; // input
> 
> This is a very simple and elegant Verilog code that infers a tristate 
> buffer. Surely I should not have to change my design to use the 3 extra 
> ports instead of just the one inout.
> 
> Also, in my *.mhs file I clearly stated that it should be an external port:
> # Global Ports
>  PORT TXRX_IO = txrx, DIR = IO # txrx connects to the 
> peripheral's                                       # TXRX_IO port
> 
> 
> If you have any clues about how this can be solved, I'll appreciate if 
> you could post them in here. Many thanks.
> 
> TonyF
> 
> 
> 
> XST error message:
> ------------------------------------------------
> Running XST synthesis ...
> INFO:MDT - The following instances are synthesized with XST. The MPD 
> option IMP_NETLIST=TRUE indicates that a NGC file is to be produced 
> using XST synthesis. IMP_NETLIST=FALSE (default) instances are not 
> synthesized. A batch file, synthesis.sh, has been created that allows 
> you to synthesize those instances in your specified synthesis tool of 
> choice.
> 
> opb_txrx_0_wrapper (opb_txrx_0) -
> C:\EDK_examples\v2pro_eval_mgt2\system.mhs:397 - Running XST synthesis
> ERROR:HDLCompilers:91 - ../hdl/opb_txrx_0_wrapper.v line 64 Module 
> 'opb_txrx' does not have a port named 'TXRX_IO_I'
> ERROR:HDLCompilers:91 - ../hdl/opb_txrx_0_wrapper.v line 65 Module 
> 'opb_txrx' does not have a port named 'TXRX_IO_O'
> ERROR:HDLCompilers:91 - ../hdl/opb_txrx_0_wrapper.v line 66 Module 
> 'opb_txrx' does not have a port named 'TXRX_IO_T'
> ERROR:MDT - HDL synthesis failed!
> 
> 
> 


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