FPGA not getting programmed

Hi, I am using a custom board design in which i have 2 FPGAs (spartan 3 xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like this: EEPROM -> FPGA1 -> FPGA2 Now the problem is that when i try to program the FPGA using JTAG, my DONE goes high, INIT_B stays high and PROG_B stays high after config, iMPACT says program succeeded but FPGA doesn't work. If i run chipscope, it says 0 cores found. Same goes when i try to program FPGAs using EEPROM. I have tried in daisy chain and even programming the FPGAs individually by disconnecting them from the chain. Now there's another dynamic to this problem, i have a previously built .bit file, when i program the FPGAs using it, they get programmed. But if i try to program the FPGAs with any other .bit file, they don't. I am clueless now and i cannot find the problem. I need help here.. Thanks regards --------------------------------------- Posted through http://www.FPGARelated.com

> Hi, > I am using a custom board design in which i have 2 FPGAs (spartan 3 > xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like > this: > > EEPROM -> FPGA1 -> FPGA2 unless the 2 FPGAs are identical, the first problem I can see here is that XCF16P (16 MBit) is not big enough to store the configuration bits for both FPGAs (11,316,864bits) .. see page 86 of UG332

>> Hi, >> I am using a custom board design in which i have 2 FPGAs (spartan 3 >> xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like >> this: >> >> EEPROM -> FPGA1 -> FPGA2 > >unless the 2 FPGAs are identical, the first problem I can see here is >that XCF16P (16 MBit) is not big enough to store the configuration >bits for both FPGAs (11,316,864bits) .. see page 86 of UG332 > The FPGAs are identical and i am trying to configure only one FPGA at the moment using JTAG. So, EEPROM signals can be ignored for now. --------------------------------------- Posted through http://www.FPGARelated.com

As you have a bit file that does work, could it be a pin constraint problem? (worng UCF file, no ucf file...) could it be that the bit file you are using is not actually the file you intended to use? (impact pickin up the bit file from an other folder?)

On Jul 14, 8:45=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I am using a custom board design in which i have 2 FPGAs (spartan 3 > xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like > this: > > EEPROM -> FPGA1 -> FPGA2 > > Now the problem is that when i try to program the FPGA using JTAG, my DON= E > goes high, INIT_B stays high and PROG_B stays high after config, iMPACT > says program succeeded but FPGA doesn't work. If i run chipscope, it says= 0 > cores found. > Same goes when i try to program FPGAs using EEPROM. I have tried in daisy > chain and even programming the FPGAs individually by disconnecting them > from the chain. > > Now there's another dynamic to this problem, i have a previously built .b= it > file, when i program the FPGAs using it, they get programmed. But if i tr= y > to program the FPGAs with any other .bit file, they don't. I am clueless > now and i cannot find the problem. > > I need help here.. > > Thanks > regards > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Had this problem about four years ago. From memory, done is connected to both FPGAs with a single pull up. If you program one device using JTAG it lets go of done but the other unprogrammed device still pulls done low and config says that it has failed. Program FPGA A. A lets go of done but B still pulls it low and the final bit of jtag says that it has failed (done is still low). Program FPGA B. B lets go of done which can now go high and B is configured correctly. Now program A again and it drives done low, configures, lets go of done and now knows that it has configured correctly. Colin

>On Jul 14, 8:45=A0pm, "salimbaba" ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >> Hi, >> I am using a custom board design in which i have 2 FPGAs (spartan 3 >> xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like >> this: >> >> EEPROM -> FPGA1 -> FPGA2 >> >> Now the problem is that when i try to program the FPGA using JTAG, my DON= >E >> goes high, INIT_B stays high and PROG_B stays high after config, iMPACT >> says program succeeded but FPGA doesn't work. If i run chipscope, it says= > 0 >> cores found. >> Same goes when i try to program FPGAs using EEPROM. I have tried in daisy >> chain and even programming the FPGAs individually by disconnecting them >> from the chain. >> >> Now there's another dynamic to this problem, i have a previously built .b= >it >> file, when i program the FPGAs using it, they get programmed. But if i tr= >y >> to program the FPGAs with any other .bit file, they don't. I am clueless >> now and i cannot find the problem. >> >> I need help here.. >> >> Thanks >> regards >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >Had this problem about four years ago. >From memory, done is connected to both FPGAs with a single pull up. If >you program one device using JTAG it lets go of done but the other >unprogrammed device still pulls done low and config says that it has >failed. > >Program FPGA A. A lets go of done but B still pulls it low and the >final bit of jtag says that it has failed (done is still low). >Program FPGA B. B lets go of done which can now go high and B is >configured correctly. >Now program A again and it drives done low, configures, lets go of >done and now knows that it has configured correctly. > >Colin Colin, i have already done that, no success. On some .bit files it gets programmed,otherwise it doesn't. I saw in FPGA editor that xilinx XST sometimes maps my signals on to INIT_B pad, was wondering if it could create problems. I am not mapping any signal on the INIT_B pad, xilinx maps it i don't know why. > --------------------------------------- Posted through http://www.FPGARelated.com

On Jul 18, 7:08=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >On Jul 14, 8:45=3DA0pm, "salimbaba" > ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >> Hi, > >> I am using a custom board design in which i have 2 FPGAs (spartan 3 > >> xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is > like > >> this: > > >> EEPROM -> FPGA1 -> FPGA2 > > >> Now the problem is that when i try to program the FPGA using JTAG, my > DON=3D > >E > >> goes high, INIT_B stays high and PROG_B stays high after config, iMPAC= T > >> says program succeeded but FPGA doesn't work. If i run chipscope, it > says=3D > > 0 > >> cores found. > >> Same goes when i try to program FPGAs using EEPROM. I have tried in > daisy > >> chain and even programming the FPGAs individually by disconnecting the= m > >> from the chain. > > >> Now there's another dynamic to this problem, i have a previously built > .b=3D > >it > >> file, when i program the FPGAs using it, they get programmed. But if i > tr=3D > >y > >> to program the FPGAs with any other .bit file, they don't. I am > clueless > >> now and i cannot find the problem. > > >> I need help here.. > > >> Thanks > >> regards > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> Posted throughhttp://www.FPGARelated.com > > >Had this problem about four years ago. > >From memory, done is connected to both FPGAs with a single pull up. If > >you program one device using JTAG it lets go of done but the other > >unprogrammed device still pulls done low and config says that it has > >failed. > > >Program FPGA A. A lets go of done but B still pulls it low and the > >final bit of jtag says that it has failed (done is still low). > >Program FPGA B. B lets go of done which can now go high and B is > >configured correctly. > >Now program A again and it drives done low, configures, lets go of > >done and now knows that it has configured correctly. > > >Colin > > Colin, > i have already done that, no success. On some .bit files it gets > programmed,otherwise it doesn't. I saw in FPGA editor that xilinx XST > sometimes maps my signals on to INIT_B pad, was wondering if it could > create problems. I am not mapping any signal on the INIT_B pad, xilinx ma= ps > it i don't know why. > > > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com- Hide quoted text - > > - Show quoted text - Which signal is being mapped on to the INIT_B pad? And where did you constrain this signal to be LOC'ed to? You are using LOC constraints on all of your I/O right? Ed McGettigan -- Xilinx Inc.

>Which signal is being mapped on to the INIT_B pad? And where did you >constrain this signal to be LOC'ed to? > >You are using LOC constraints on all of your I/O right? > >Ed McGettigan >-- >Xilinx Inc. > It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am not using LOC constraints on all the IOs .. --------------------------------------- Posted through http://www.FPGARelated.com

On Jul 18, 8:32=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >Which signal is being mapped on to the INIT_B pad? =A0And where did you > >constrain this signal to be LOC'ed to? > > >You are using LOC constraints on all of your I/O right? > > >Ed McGettigan > >-- > >Xilinx Inc. > > It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am n= ot > using LOC constraints on all the IOs .. =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Creating a design to be downloaded into a board without fully LOC constraining all of the IO is just asking for trouble and can potentially damage the FPGA or another device on the board. You need to fix this ASAP and it will very likely resolve your original problem. Ed McGettigan -- Xilinx Inc.

>On Jul 18, 8:32=A0am, "salimbaba" ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >> >Which signal is being mapped on to the INIT_B pad? =A0And where did you >> >constrain this signal to be LOC'ed to? >> >> >You are using LOC constraints on all of your I/O right? >> >> >Ed McGettigan >> >-- >> >Xilinx Inc. >> >> It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am n= >ot >> using LOC constraints on all the IOs .. =A0 =A0 >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >Creating a design to be downloaded into a board without fully LOC >constraining all of the IO is just asking for trouble and can >potentially damage the FPGA or another device on the board. > >You need to fix this ASAP and it will very likely resolve your >original problem. > >Ed McGettigan >-- >Xilinx Inc. > okay i'll fix it and then update you. Thanks Regards --------------------------------------- Posted through http://www.FPGARelated.com

On Jul 19, 3:20=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Jul 18, 8:32=A0am, "salimbaba" > > <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > > >Which signal is being mapped on to the INIT_B pad? =A0And where did yo= u > > >constrain this signal to be LOC'ed to? > > > >You are using LOC constraints on all of your I/O right? > > > >Ed McGettigan > > >-- > > >Xilinx Inc. > > > It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am= not > > using LOC constraints on all the IOs .. =A0 =A0 > > > --------------------------------------- =A0 =A0 =A0 =A0 > > Posted throughhttp://www.FPGARelated.com > > Creating a design to be downloaded into a board without fully LOC > constraining all of the IO is just asking for trouble and can > potentially damage the FPGA or another device on the board. > > You need to fix this ASAP and it will very likely resolve your > original problem. > > Ed McGettigan > -- > Xilinx Inc. Ed's point is very much valid. You should fully Constrain all the IO signals in your design before you start implementation. I have faced this problem long back. Every board has specific pins for JTAG interface, but if you don't constrain your IOBs, it may end up in using these JTAG specific IO's by your normal logic IO signals. -- vasu

On Jul 19, 12:54=A0am, vasu <vasu.devun...@gmail.com> wrote: > On Jul 19, 3:20=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Jul 18, 8:32=A0am, "salimbaba" > > > <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > > > >Which signal is being mapped on to the INIT_B pad? =A0And where did = you > > > >constrain this signal to be LOC'ed to? > > > > >You are using LOC constraints on all of your I/O right? > > > > >Ed McGettigan > > > >-- > > > >Xilinx Inc. > > > > It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i = am not > > > using LOC constraints on all the IOs .. =A0 =A0 > > > > --------------------------------------- =A0 =A0 =A0 =A0 > > > Posted throughhttp://www.FPGARelated.com > > > Creating a design to be downloaded into a board without fully LOC > > constraining all of the IO is just asking for trouble and can > > potentially damage the FPGA or another device on the board. > > > You need to fix this ASAP and it will very likely resolve your > > original problem. > > > Ed McGettigan > > -- > > Xilinx Inc. > > Ed's point is very much valid. You should fully Constrain all the IO > signals in your design =A0before you start implementation. I have faced > this problem long back. Every board has specific pins for JTAG > interface, but if you don't constrain your IOBs, it may end up in > using these JTAG specific IO's by your normal logic IO signals. > > -- vasu- Hide quoted text - > > - Show quoted text - Some older FPGA families did not use dedicated JTAG pins, but all modern FPGAs do have dedicated JTAG pins. Ed McGettigan -- Xilinx Inc.

On Jul 20, 5:19=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Jul 19, 12:54=A0am, vasu <vasu.devun...@gmail.com> wrote: > > > > > > > > > > > On Jul 19, 3:20=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Jul 18, 8:32=A0am, "salimbaba" > > > > <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > > > > >Which signal is being mapped on to the INIT_B pad? =A0And where di= d you > > > > >constrain this signal to be LOC'ed to? > > > > > >You are using LOC constraints on all of your I/O right? > > > > > >Ed McGettigan > > > > >-- > > > > >Xilinx Inc. > > > > > It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And = i am not > > > > using LOC constraints on all the IOs .. =A0 =A0 > > > > > --------------------------------------- =A0 =A0 =A0 =A0 > > > > Posted throughhttp://www.FPGARelated.com > > > > Creating a design to be downloaded into a board without fully LOC > > > constraining all of the IO is just asking for trouble and can > > > potentially damage the FPGA or another device on the board. > > > > You need to fix this ASAP and it will very likely resolve your > > > original problem. > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > Ed's point is very much valid. You should fully Constrain all the IO > > signals in your design =A0before you start implementation. I have faced > > this problem long back. Every board has specific pins for JTAG > > interface, but if you don't constrain your IOBs, it may end up in > > using these JTAG specific IO's by your normal logic IO signals. > > > -- vasu- Hide quoted text - > > > - Show quoted text - > > Some older FPGA families did not use dedicated JTAG pins, but all > modern FPGAs do have dedicated JTAG pins. > > Ed McGettigan > -- > Xilinx Inc. I faced this problem in Virtex-6 FPGA based design.

"Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:1b9eb6a7-70d2-44fa-9710-0c2eb22262db@t8g2000prm.googlegroups.com... >Some older FPGA families did not use dedicated JTAG pins, but all >modern FPGAs do have dedicated JTAG pins. I guess modern FPGA's have just sw dedicated jtag pins.. At least Altera's can be used as IO through megafunctions (like sld_virtual_jtag). I agree that's the way to do it instead of letting them loose as generic io.