General question about soft CPUs

  • Permalink
  • submit to reddit
  • Email
  • Follow


I am looking for some information about how "real" this soft CPU
technology is.  I'm working with someone who has become enamored with
the "soft CPU" concept from the FPGA vendors.  I have a number of what
seem to me to be "gotta know" questions about this technology, and I
don't know how to get them answered. There are big picture questions
like:

- What are the compelling reasons to go this route?
- If we take this path, can it be made to *really* work, i.e. never
fail from one in a billion type errors?
- How much longer will it take to do it this way compared to the "old"
way of using a separate processor and FPGA?

Then I have small picture questions like:

- If you need to add peripherals (like UARTs, PWM contoller,
etc., etc.) how well does this work?
- Is the whole development environment reasonable?

I looked around on the web, and there sure is a lot of marketing
material, especially from Xilinx and Altera, but that's not what I'm
looking for.  Do you know anywhere I could get a description of how a
real commercial project has gone for somebody, so that I can get some
of my questions answered?

Thanks!
Steve

0
Reply smkraft (1) 4/12/2005 5:41:40 PM

See related articles to this posting


Hi Steve,

    The Nios Community Forum can provide you answers to your question
on the Nios II, Nios processors, their associated development
environment, tool chain support, RTOS's and peripherals from Altera
Corp. You can access it at www.niosforum.org.

Hope this helps.

Subroto Datta
Altera Corp.

Steve wrote:
> I am looking for some information about how "real" this soft CPU
> technology is.  I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors.  I have a number of
what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
>
> - What are the compelling reasons to go this route?
> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?
> - How much longer will it take to do it this way compared to the
"old"
> way of using a separate processor and FPGA?
>
> Then I have small picture questions like:
>
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?
> - Is the whole development environment reasonable?
>
> I looked around on the web, and there sure is a lot of marketing
> material, especially from Xilinx and Altera, but that's not what I'm
> looking for.  Do you know anywhere I could get a description of how a
> real commercial project has gone for somebody, so that I can get some
> of my questions answered?
> 
> Thanks!
> Steve

0
Reply Subroto 4/12/2005 5:48:47 PM

"Steve" <smkraft@pacbell.net> schrieb im Newsbeitrag
news:1113327700.042531.314340@l41g2000cwc.googlegroups.com...
> I am looking for some information about how "real" this soft CPU
> technology is.  I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors.  I have a number of what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
>
> - What are the compelling reasons to go this route?

1) no obsolence
2) build your system with the peripherals and functions you need
3) design hardware after its has been manufactured to speed up time to
market, the hardware is only bitstream and can be updated softly, also you
can rework early design errors without the PCB changes
4) flexibility, design to be future safe, new hardware features can be added
after product hardware is manufactured
5) etc..

> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?
almost nothing is failsafe, and extenal CPU and FPGA are possible evenso
likely to fail

> - How much longer will it take to do it this way compared to the "old"
> way of using a separate processor and FPGA?

not longer, but how much faster would be appropriate.
get some Eval board for either NIOS-II or EDK, and you are writing normal C
programs as soon as you the board and installed software

> Then I have small picture questions like:
>
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?

a few mouse clicks. the environment builds the C include files and libraries
for you

> - Is the whole development environment reasonable?

depends on your understanding of reasonable :)
yes its ready and useable, but one could wish more..

> I looked around on the web, and there sure is a lot of marketing
> material, especially from Xilinx and Altera, but that's not what I'm
> looking for.  Do you know anywhere I could get a description of how a
> real commercial project has gone for somebody, so that I can get some
> of my questions answered?
>
> Thanks!
> Steve
>

there are quite a many commercial products aroung actually I think, but
there is no list of them.

I started with new job at www.eubus.net Jan 2005, and after that Microblaze
has been used in two different redesigns (both defenetly commercial
products), besides those
http://www.hydraxc.com
is full product line totally oriented to the use of SoftCore CPU's

even though there are may be not so many references to the commercial use of
soft to core CPUs yet I am very positive that they are used more widely as
you may guess (from what is visible and public), I think the FPGA vendors
actually have some feadback about how many FPGA designs use softcore CPUs,
and this % is gorwing FAST, very FAST.

Antti














0
Reply Antti 4/12/2005 5:55:15 PM

Steve wrote:
> I am looking for some information about how "real" this soft CPU
> technology is.  I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors.  I have a number of
what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
>

As real as anything else one might want to put into an FPGA.

> - What are the compelling reasons to go this route?

There are some reasons that drive this, depending on developer though

Control, previuosly I used ARM7TDMI external, as the FPGA got more
capability & did more work, the system was stuck with same external cpu
that was starting to become a bottleneck. Soft core cpus allow for the
EE to get control of the system and insert cpu power where it's needed
rather than depending on the ASIC supplier to help out. The worlds
greatest cpu isn't much use on the ouitside if you want it inside for
fine grain control. Some cpus are so tiny (PicoBlaze) they are hardly
recognizeable to a manager, but they may be perfectly fine for doing
some odd job FSMs. More interesting soft cpus may be just as capable as
many external cpus (<< 200MHz that is), but you get some options that
aren't possible on the outside. You could hide the soft cpu deeply, not
mention it it to marketing or the competition, and the binary that runs
on it can be merged into the FPGA bitfile, both the design, the start
up code and initial data.

Downsides include less well developed tools but thats improving with
the gcc kit being everywhere, less big companies to hold hands, less
training etc.

Also the game has really just started, as FPGAs replace ASICs, I think
we will see less opportunites for MIPs/ARM the traditional embedded
suppliers. PPC though gets it both ways since it can be an external
part or available as internal hard core for Xilinx (and to a lesser
extent ARM with Altera).

Upside usually no serious licence fee, you may even get permission to
ASIC if you want for a smidgeon compared to dealing with ARM.

Some other possibilities also include customizing the instruction set
with new opcodes that might have a huge performance boost over doing it
purely in SW even in an external much faster cpu. Or do same with a bit
more distance hook up your engines to cpu ports or links or busses.

There will come a time when people will think nothing of it and why
should the cpu be on the outside with so little access to the
internals. But there may still be use for an external cpu to hook up
with other system components.

> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?
> - How much longer will it take to do it this way compared to the
"old"
> way of using a separate processor and FPGA?
>

If you forbid the use of soft core cpus, some projects may well take
longer if thats what they need.

> Then I have small picture questions like:
>
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?
> - Is the whole development environment reasonable?
>
> I looked around on the web, and there sure is a lot of marketing
> material, especially from Xilinx and Altera, but that's not what I'm
> looking for.  Do you know anywhere I could get a description of how a
> real commercial project has gone for somebody, so that I can get some
> of my questions answered?
>
> Thanks!
> Steve


just my opinions

regards

johnjakson at usa dot com
transputer2 at yahoo dot com

0
Reply JJ 4/12/2005 7:23:03 PM

Steve wrote:

> I am looking for some information about how "real" this soft CPU
> technology is.  I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors.  I have a number of what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
> 
> - What are the compelling reasons to go this route?

That depends very much on your product, market, and definition process.
There are both advantages and disadvantages in SoftCPU.

+You can roll almost anything that marketing dreams up [if you can keep 
up with their changes :) ]

+Systems that need high bandwidth, sepecialised peripheral coupling can
work very well in soft-cpu

+SoftCPUs cover a very wide range: Some of the tiny ones, can run from 
block ram, and can be very good INIT and handshake problem solvers.

-You will quite often need "next size" FPGA to include the CPU.
[The FPGA vendors love this feature.. ]

-It is not actually a single chip solution : You need the loader PROM,
and some form of code execution memory. That can mean wide.high speed
data busses, and many EMC issues.
It is also not trivial to select and source that execution memory.
Again, you can "next size" the FPGA, to get enough Block Ram to run
all code on chip.

-Power consumption can take quite a hit. Static Icc on newest FPGAs is 
terrible, when compared with Std Microcontrollers.


You can, of course, have more than one controller in a design.

You might use a small uC for WDOG, Init, ADC, BrownOut, and power save 
tasks, and a larger SoftCPU, or choose one of the new larger FLASH uC,
and load the (now smaller) FPGA from that.

For uC <-> FPGA interface you can choose parallel, or the newer faster 
serial interfaces.


> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?

This is what I'd call mature technology.
Field reliability is another area in itself...

> - How much longer will it take to do it this way compared to the "old"
> way of using a separate processor and FPGA?
> 
> Then I have small picture questions like:
> 
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?

Very well, if the peripheral mix is outside the typical uC.
If you want 64 PWM channels, or special serials etc.

Just don't try and add ADCs as peripherals, or 32KHz clock
oscillators, or Brownout detectors..... :)

-jg

0
Reply Jim 4/12/2005 7:24:01 PM

Antti Lukats wrote:
> "Steve" <smkraft@pacbell.net> schrieb im Newsbeitrag
> news:1113327700.042531.314340@l41g2000cwc.googlegroups.com...
> 
>>I am looking for some information about how "real" this soft CPU
>>technology is.  I'm working with someone who has become enamored with
>>the "soft CPU" concept from the FPGA vendors.  I have a number of what
>>seem to me to be "gotta know" questions about this technology, and I
>>don't know how to get them answered. There are big picture questions
>>like:
>>
>>- What are the compelling reasons to go this route?
> 
> 
> 1) no obsolence
> 2) build your system with the peripherals and functions you need
> 3) design hardware after its has been manufactured to speed up time to
> market, the hardware is only bitstream and can be updated softly, also you
> can rework early design errors without the PCB changes
> 4) flexibility, design to be future safe, new hardware features can be added
> after product hardware is manufactured
> 5) etc..

As a practical matter, don't all of these points also apply to an 
external uC with an FPGA as a peripheral? Also, I'm a little perplexed 
by point 1 - no obsolescence  - don't FPGAs families become obsolete 
just like anything else? Or do you mean something else?

-Jeff
0
Reply Jeff 4/13/2005 2:37:00 AM

Jeff Cunningham wrote:
> Antti Lukats wrote:
> 
>> "Steve" <smkraft@pacbell.net> schrieb im Newsbeitrag
>> news:1113327700.042531.314340@l41g2000cwc.googlegroups.com...
>>
>>> I am looking for some information about how "real" this soft CPU
>>> technology is.  I'm working with someone who has become enamored with
>>> the "soft CPU" concept from the FPGA vendors.  I have a number of what
>>> seem to me to be "gotta know" questions about this technology, and I
>>> don't know how to get them answered. There are big picture questions
>>> like:
>>>
>>> - What are the compelling reasons to go this route?
>>
>>
>>
>> 1) no obsolence
>> 2) build your system with the peripherals and functions you need
>> 3) design hardware after its has been manufactured to speed up time to
>> market, the hardware is only bitstream and can be updated softly, also 
>> you
>> can rework early design errors without the PCB changes
>> 4) flexibility, design to be future safe, new hardware features can be 
>> added
>> after product hardware is manufactured
>> 5) etc..
> 
> 
> As a practical matter, don't all of these points also apply to an 
> external uC with an FPGA as a peripheral? Also, I'm a little perplexed 
> by point 1 - no obsolescence  - don't FPGAs families become obsolete 
> just like anything else? Or do you mean something else?

I think the point here is that it gives high confidence that today's 
soft CPU design, targeted to say a Spartan3, will still be able to be 
synthesised into a spartan10, XX years down the track.

In contrast, developing a product with a fixed silicon embedded 
processor + peripheral set - if it just so happens that you choose a 
CPU+peripheral combo that doesn't sell so well, there's every likelihood 
it will be end-of-lifed before too long.

Remembering of course that you don't just buy "a coldfire" (or an 8051, 
or whatever), but rather devices in this space are bundled with various 
options on the silicon - the number of combinations is finite, and you 
are at the mercy of the silicon providor to continue supplying *that 
specific combo* into the future.  FPGAs being generic means that you can 
be sure to implement the same digital system (eg CPU + peripheral combo) 
for as long as you want.

John






> 
> -Jeff
0
Reply John 4/13/2005 3:22:15 AM

>>>I am looking for some information about how "real" this soft CPU
>>>technology is.  I'm working with someone who has become enamored with
>>>
>>>- What are the compelling reasons to go this route?
>>
>> 1) no obsolence
>> 2) build your system with the peripherals and functions you need
>> 3) design hardware after its has been manufactured to speed up time to
>> market, the hardware is only bitstream and can be updated softly, also 
>> you
>> can rework early design errors without the PCB changes
>> 4) flexibility, design to be future safe, new hardware features can be 
>> added
>> after product hardware is manufactured
>> 5) etc..
>
> As a practical matter, don't all of these points also apply to an external 
> uC with an FPGA as a peripheral? Also, I'm a little perplexed by point 1 - 
> no obsolescence  - don't FPGAs families become obsolete just like anything 
> else? Or do you mean something else?
>
> -Jeff

- Most FPGAs run in high-volume, uCs often have a lot of drivates, the ones 
that are not selling well are often canceled.
- If the FPGA is finally obselete, it will be pretty easy to change the 
design to a newer product, at least if you have the VHDL-source of the core.
- In a way you are also right that this is a marketing argument, especially 
if you have no source-code. You could e.g. say, that "Nios I" is already 
obsolete, i.e. no longer good supported...

I think two further important advantages of soft-cores are:
5) reduced board-space
6) reduced costs (if the design is right. if it is not, you can run into 
additional costs by the need of a larger FPGA.)

Thomas

www.entner-electronics.com


0
Reply Thomas 4/13/2005 12:47:42 PM
comp.arch.fpga 18395 articles. 19 followers. Post

7 Replies
153 Views

Similar Articles

[PageSpeed] 44


  • Permalink
  • submit to reddit
  • Email
  • Follow


Reply:

Similar Artilces:

general question question is fun to answeder
how is javascrip different than java and c#? chmm On 23/02/11 19:26, Robin wrote: > how is javascrip different than java and c#? "javascrip" is a made up word. "java" and "c#" are programming languages. Homework answers are not found in newsgroups. Rgds Denis McMahon On Wed, 23 Feb 2011 11:26:55 -0800 (PST), Robin wrote: > how is javascrip different than java and c#? > chmm These questions you ask are typical of students looking for a quick answer because they're too lazy to use a search engine. ...

two graphics questions and one general question
I am trying to figure out how to place styled arrowheads at the ends of axes. The arrowheads need to match those in Adobe Illustrator. I can create each type of arrowhead as a polygon, but I cannot figure out how to place the polygons correctly. I am also trying to figure out how to place tick labels at a particular distance from the axes (i.e, 3pts below the x-axis and 2 pts to the left of the y-axis.) I need to be able to center the labels under or to the side of the ticks (accounting for negative signs). Finally, when I use Plot[....], unless I include the ImageSize option, the ...

a general question
what linux is the best for a regular computer user? --- cinganjing@me.com On Feb 17, 7:09=A0pm, "cinganj...@me.com" <cinganj...@me.com> wrote: > what linux is the best for a regular computer user? > > --- > cinganj...@me.com by the way excuse me if i posted this in the wrong place --- cinganjing @ me.com cinganjing@me.com wrote: > what linux is the best for a regular computer user? > Depends on what regular means I am pretty happy with debian.. ...but mint is possibly better for multimedia. Now unbuntu seems to have developed delusions of grandeur. ...

A general question
On average, how many lines of code does a software engineer write every day? Somebody says 30-40 lines. It is true? Thanks. junw2000@gmail.com wrote: > On average, how many lines of code does a software engineer write > every day? Counting [average] LOC is meaningless. A software engineer does much more than that. There are sometimes _weeks_ when I (a professional software engineer) write no code at all, while being quite productive (if you ask my bosses, anyway). > Somebody says 30-40 lines. It is true? Thanks. If he/she says he/she writes so much, it's probably true. It ...

general questions
As I was taking my c128d apart, I noticed again how ineffective the strain relief on the keyboard cable is. It's hard as a rock and too short. The cable has a kink in it where it bends at 90 degrees instead of being relieved. Has anyone experienced failure of this cable, especially at this point? And no, I didn't bend the cable that way, it was shipped to me that way. 2nd, why do the C= drives have a removable Commodore logo "badge" on the top? Was C= thinking they could sell Atari drives and just swap the logo? All 1541s I've seen have it and the SFD-1001. VIC-1541s (...

general question...
Hi to all out there I am trying to develop a feedforward network mlp with 7 inputs and 2 outputs. Since the optimum number of hidden layers and neurons can only be found by trial and error methods, I assume that I have to construct all available network architectures and find the test error or training error of each one. If this is the case the question is: how should I initially train all these networks in order to determine the best of them? Should I stuck into one training method with same number of iterations,same learning rate for all of them? If I choose different training method or le...

General questions
Dear folks, I've been interested in Ruby for quite a while now, but since I'm unfortunately not doing it professionally, I don't have time to get deeper in it, which is frustrating me quite a bit. That's why I've decided to start looking for a Ruby developer position. Since I've only coded Ruby for my own pleasure, I was wondering what the professional environment in Ruby looks like. Ruby is also said to be pretty maintainable. But since I've only worked professionally in Java, I somehow couldn't agree with that one. When I code for myself, I just have a few c...

General question
Hello, I've just started to use IMAP folders, so I don't know much about them. It is my understanding that, unlike POP3, IMAP folders are located on the server. So if I get a message in my IMAP Inbox that contains a virus, it cannot harm my computer, even if I read it, until I deliver it to my e-mail client using POP3. Am I correct? Thank you, -- Peter Afonin Peter Afonin wrote: > Hello, > > I've just started to use IMAP folders, so I don't know much about them. > > It is my understanding that, unlike POP3, IMAP folders are located on the > server. S...

general question
Hello all, does a firewall only block messages from the outside i.e. IP source not equal to IP_of_firewall or does it also block internal traffic? E.g. if port 5000 is blocked, will telnet own_ip_address 5000 succeed or not? Tnx in advance for any answer that can help. Hi, Claeys Marc <marc.claeys@alcatel.be> wrote: > E.g. if port 5000 is blocked, will telnet own_ip_address 5000 > succeed or not? Depends on the firewall. Greetings, Jens "Claeys Marc" <marc.claeys@alcatel.be> wrote in message news:c8s1t2$vi8$1@news.alcatel.fr... > Hello all, > >...

General questions
New to using databases that are NOT Access. New to MS SQL Server. I'd like help understanding some concepts. Firstly, I'd like to know how to connect to a database using MS SQL Server on a remote web server using Windows XP; I know the IP and have the username and password to connect...but what program do I use? Suggestions, appreciated. Secondly, I'd like to make changes to the remote database - anyone suggest programs to use? Regards, OZ Oz (ozymandias@gmail.com) writes: > New to using databases that are NOT Access. New to MS SQL Server. I'd > like help understandin...

General question
Hi Group, I am a little hesitant to ask this, after having read the "your question is less lively than a dead parrot answer!", but here goes. (Read thru the Faq, may have missed this, in which case would be happy to be steered correctly.) Could someone give me an understanding why .......... printf("foobar") ........ without the directive #include<stdio> still prints, but does so (in Xcode 2.2) with a warning. Clearly, I am trying to gain an overview of C, and am obviously missing something about compiling/linking etc. Thanks I realize I should have said,...

general question
Using 9i SQL on HR employees table, perform SELECT LAST_NAME FROM EMPLOYEES why do the names sort out alphabetically asc? Is there a default working? Pure chance. Don't rely on it. Jim "sfk" <stefano1@att.net> wrote in message news:3Q6P9.81319$hK4.6680146@bgtnsc05-news.ops.worldnet.att.net... > Using 9i SQL on HR employees table, perform > > SELECT LAST_NAME FROM EMPLOYEES > > why do the names sort out alphabetically asc? Is there a default > working? > > > I know it is not the way the data is actually stored. If I do a "select *&qu...

General question...
Is VxWorks 100% POSIX (RT) system? -- Non sibi! Wlad [UR3LOS] TNX! Drawing my attention to QNX... -- Non sibi! Wlad [UR3LOS] "Joe Durusau" <durusau@bellsouth.net> ???????/???????? ? ???????? ?????????: news:3F40BB92.7080402@bellsouth.net... > No. It has POSIX stuff built in, but it is not 100% POSIX. > > Speaking only for myself, > > Joe Durusau > > > Vladimir Los wrote: > > Is VxWorks 100% POSIX (RT) system? > > > > -- > > > > Non sibi! > > Wlad [UR3LOS] > > > > > > ...

General question :
I have a system using Sendmail and Dovecot for pop/imap 1) I can see, on most documentations, procmail as also spam filter... and sending email... As far as I can see, sendmail can send emails perfectly ? so should I use Procmail ? 2) I wish to handle several domain name with ONE sendmail machine. I am also using Squirrelmail. But as far as I can see, Squirrelmail can only manage ONE domain name ? - How can I be able to connect and send email either : user1@domain1.com or user1@domain2.com ? Thanks and regards, On 03/17/08 10:29, Steve wrote: > I have a system using Sendmail and Doveco...

General question
How much do you think it costs, to develope a brand new OS - like VISTA? In article <VicVg.47679$vX5.32300@bignews8.bellsouth.net>, "zara" <zspook@fisheaven.net> wrote: > How much do you think it costs, to develope a brand new OS - like VISTA? Heh. This post invites some great replies. "zara" <zspook@fisheaven.net> stated in post VicVg.47679$vX5.32300@bignews8.bellsouth.net on 10/5/06 11:38 AM: > How much do you think it costs, to develope a brand new OS More money than I will ever see. :) > - like VISTA? Never used it. I will let...

general questions
Doing some reading in attempt to get acclimated with 'debugging techniques among other things (ie assembly, pipeling, tomasolo etc.)', more specifically trying to educate myself on 'software' (backgound is physics. bs in physics). so i'm reading this text and i've tried select questions per chapter but here is some confusion on my part. -------- 1 -------- why is it that optimized code consume more memory? my thoughts were ... if the compiler is 'ripping' out code, how does that equate to more memory usage. i'd think the memory should decrease? --------...

a general question
I'm a beginner in this field so forgive me if what seems interesting for me can seem stupid for others. I'm approaching the fpga field cause i' ve read many times that the fpga can reduce the time to market and reduce the costs of the system for low volume applications. Surfing on the web i can find easily PC-104 platform for more or less 100$ that have a 300MHz cpu clock etc etc. If i search for an fpga board with the same price i will never reach comparable performance, or quantity of hardware. So i would like to know which are the markets or the applications where an fpga can...

General question
Hi I'm a Linux user and want to learn something about Solaris. Where can I find information about Solaris in general (history what about OpenSolaris ...) and Solaris im comparison to Linux? With kind regards Markus -- ------------------------------------------------------- Try this: SCA the Smart Class Archive for PHP http://www.project-sca.org ------------------------------------------------------- On Mon, 11 Jul 2005, Markus L. wrote: > I'm a Linux user and want to learn something about Solaris. Always nice to see an open mind! > Where can I find information about Solar...

A General Question
My ISP has a great anti-spam system and blocks out 99 percent of the garbage. But every once in a while I'll take a look at something I'm pretty sure is harmless. What I usually find is email full of nonsensical garbage mixed in with some message-- sometimes, it's just garbage. I'm wondering why so much spam has all that silly crap mixed in with it. Does anybody have a clue? Ron yep, some of it will take you right to a virus or spyware "Ron Hubbard" <hubbard-ron@hotmail.com> wrote in message news:2p4vfiFguunlU1@uni-berlin.de... > My ISP has a great anti-...

General Question
To Whom it May Concern, How do we get notified when a SAS release is out of support, that is no-fixes will be supplied for a particular release ? How do we get notified when a new SAS release(GAed) is available for customer use ? Angelo Grotticelli Talbots - Systems Center office: (813) 829-6036 e-mail: Angelo.Grotticelli@Talbots.com Subscribe to TS-News via http://support.sas.com/techsup/news/tsnews.html Regards - Jim. -- .. . . . . . . . . . . . . . . . Jim Groeneveld, MSc. Biostatistician Science Team Vitatron B.V. Meander 1051 682...

This is general Questions?
Dear Friends, Where can I get the ls source code. Please anyboby already aware means that tell to me. I have been searching since two days,but I was unable to get the clear source code of ls. anyone help me. by Vellingiri. -- Posted via http://www.ruby-forum.com/. On 20 Sep 2007, at 18:08, Vellingiri Arul wrote: > Dear Friends, > Where can I get the ls source code. > Please anyboby already aware means that tell to me. > I have been searching since two days,but I was unable to get the clear > source code of ls. > anyone help me. > > by > Vellingiri. ...

A few general questions
Hi ammal I have a few questions... After ripping the 16 bit sound upgrade out of our non-working motherboard (see other thread), I clunked it into my machine to upgrade my sound. But now there is something screwy: After a while the speaker emits these funny clicking noises, and if I let the system make a beep it is very noisy and distorted. Anyone have any idea what could be the cause? I wanted to ask another wuestion too now, but I forgot... Ciao! Samuel -- Samuel Kock A clean and tidy desk is a sign of a *very* sick mind. skok wrote: > Hi ammal > > I have a few questions......

general questions
I am confused by the process by which a digital certificate certifies or binds the public key of the entity specified within the digital certificate to the entities name or website also I suppose specified within the certificate. 1. How is the digital certificate sent? If A sends a PK to B where is the digital certificate in this process? Is it sent separately? I assume it is encrypted with the private key of the CA and so anyone with the public key of the CA(usually included in a browser I guess) can decrypt it. IF it were sent separately wouldn't that be a risk of some sort? Is the PK se...

general question!
Hi! I have a question...I want to scan through a matrixB(see below) and link it to its corresponding index in column1 of matrixA! MatrixA has all the information but I want to end up having a something like A1=[1 22 1 27 1 29] A2=[2 26 2 30 2 31] A3= [3 23 3 25 3 28 3 32]; MatrixA=[ 1 22 3 23 1 24 3 25 2 26 1 27 3 28 1 29 2 30 2 31 3 32] MatrixB=[22 23 24 25 26 27 28 29 30 31 32] thanks in advance Larry Larry wrote: > Hi! I have a question...I want to scan through a > matrixB(see below) and link it to its correspo...