General question about soft CPUs

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I am looking for some information about how "real" this soft CPU
technology is.  I'm working with someone who has become enamored with
the "soft CPU" concept from the FPGA vendors.  I have a number of what
seem to me to be "gotta know" questions about this technology, and I
don't know how to get them answered. There are big picture questions
like:

- What are the compelling reasons to go this route?
- If we take this path, can it be made to *really* work, i.e. never
fail from one in a billion type errors?
- How much longer will it take to do it this way compared to the "old"
way of using a separate processor and FPGA?

Then I have small picture questions like:

- If you need to add peripherals (like UARTs, PWM contoller,
etc., etc.) how well does this work?
- Is the whole development environment reasonable?

I looked around on the web, and there sure is a lot of marketing
material, especially from Xilinx and Altera, but that's not what I'm
looking for.  Do you know anywhere I could get a description of how a
real commercial project has gone for somebody, so that I can get some
of my questions answered?

Thanks!
Steve

0
Reply smkraft (1) 4/12/2005 5:41:40 PM

See related articles to this posting

Hi Steve,

    The Nios Community Forum can provide you answers to your question
on the Nios II, Nios processors, their associated development
environment, tool chain support, RTOS's and peripherals from Altera
Corp. You can access it at www.niosforum.org.

Hope this helps.

Subroto Datta
Altera Corp.

Steve wrote:
> I am looking for some information about how "real" this soft CPU
> technology is.  I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors.  I have a number of
what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
>
> - What are the compelling reasons to go this route?
> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?
> - How much longer will it take to do it this way compared to the
"old"
> way of using a separate processor and FPGA?
>
> Then I have small picture questions like:
>
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?
> - Is the whole development environment reasonable?
>
> I looked around on the web, and there sure is a lot of marketing
> material, especially from Xilinx and Altera, but that's not what I'm
> looking for.  Do you know anywhere I could get a description of how a
> real commercial project has gone for somebody, so that I can get some
> of my questions answered?
> 
> Thanks!
> Steve

0
Reply Subroto 4/12/2005 5:48:47 PM

"Steve" <smkraft@pacbell.net> schrieb im Newsbeitrag
news:1113327700.042531.314340@l41g2000cwc.googlegroups.com...
> I am looking for some information about how "real" this soft CPU
> technology is.  I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors.  I have a number of what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
>
> - What are the compelling reasons to go this route?

1) no obsolence
2) build your system with the peripherals and functions you need
3) design hardware after its has been manufactured to speed up time to
market, the hardware is only bitstream and can be updated softly, also you
can rework early design errors without the PCB changes
4) flexibility, design to be future safe, new hardware features can be added
after product hardware is manufactured
5) etc..

> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?
almost nothing is failsafe, and extenal CPU and FPGA are possible evenso
likely to fail

> - How much longer will it take to do it this way compared to the "old"
> way of using a separate processor and FPGA?

not longer, but how much faster would be appropriate.
get some Eval board for either NIOS-II or EDK, and you are writing normal C
programs as soon as you the board and installed software

> Then I have small picture questions like:
>
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?

a few mouse clicks. the environment builds the C include files and libraries
for you

> - Is the whole development environment reasonable?

depends on your understanding of reasonable :)
yes its ready and useable, but one could wish more..

> I looked around on the web, and there sure is a lot of marketing
> material, especially from Xilinx and Altera, but that's not what I'm
> looking for.  Do you know anywhere I could get a description of how a
> real commercial project has gone for somebody, so that I can get some
> of my questions answered?
>
> Thanks!
> Steve
>

there are quite a many commercial products aroung actually I think, but
there is no list of them.

I started with new job at www.eubus.net Jan 2005, and after that Microblaze
has been used in two different redesigns (both defenetly commercial
products), besides those
http://www.hydraxc.com
is full product line totally oriented to the use of SoftCore CPU's

even though there are may be not so many references to the commercial use of
soft to core CPUs yet I am very positive that they are used more widely as
you may guess (from what is visible and public), I think the FPGA vendors
actually have some feadback about how many FPGA designs use softcore CPUs,
and this % is gorwing FAST, very FAST.

Antti














0
Reply Antti 4/12/2005 5:55:15 PM

Steve wrote:
> I am looking for some information about how "real" this soft CPU
> technology is.  I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors.  I have a number of
what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
>

As real as anything else one might want to put into an FPGA.

> - What are the compelling reasons to go this route?

There are some reasons that drive this, depending on developer though

Control, previuosly I used ARM7TDMI external, as the FPGA got more
capability & did more work, the system was stuck with same external cpu
that was starting to become a bottleneck. Soft core cpus allow for the
EE to get control of the system and insert cpu power where it's needed
rather than depending on the ASIC supplier to help out. The worlds
greatest cpu isn't much use on the ouitside if you want it inside for
fine grain control. Some cpus are so tiny (PicoBlaze) they are hardly
recognizeable to a manager, but they may be perfectly fine for doing
some odd job FSMs. More interesting soft cpus may be just as capable as
many external cpus (<< 200MHz that is), but you get some options that
aren't possible on the outside. You could hide the soft cpu deeply, not
mention it it to marketing or the competition, and the binary that runs
on it can be merged into the FPGA bitfile, both the design, the start
up code and initial data.

Downsides include less well developed tools but thats improving with
the gcc kit being everywhere, less big companies to hold hands, less
training etc.

Also the game has really just started, as FPGAs replace ASICs, I think
we will see less opportunites for MIPs/ARM the traditional embedded
suppliers. PPC though gets it both ways since it can be an external
part or available as internal hard core for Xilinx (and to a lesser
extent ARM with Altera).

Upside usually no serious licence fee, you may even get permission to
ASIC if you want for a smidgeon compared to dealing with ARM.

Some other possibilities also include customizing the instruction set
with new opcodes that might have a huge performance boost over doing it
purely in SW even in an external much faster cpu. Or do same with a bit
more distance hook up your engines to cpu ports or links or busses.

There will come a time when people will think nothing of it and why
should the cpu be on the outside with so little access to the
internals. But there may still be use for an external cpu to hook up
with other system components.

> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?
> - How much longer will it take to do it this way compared to the
"old"
> way of using a separate processor and FPGA?
>

If you forbid the use of soft core cpus, some projects may well take
longer if thats what they need.

> Then I have small picture questions like:
>
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?
> - Is the whole development environment reasonable?
>
> I looked around on the web, and there sure is a lot of marketing
> material, especially from Xilinx and Altera, but that's not what I'm
> looking for.  Do you know anywhere I could get a description of how a
> real commercial project has gone for somebody, so that I can get some
> of my questions answered?
>
> Thanks!
> Steve


just my opinions

regards

johnjakson at usa dot com
transputer2 at yahoo dot com

0
Reply JJ 4/12/2005 7:23:03 PM

Steve wrote:

> I am looking for some information about how "real" this soft CPU
> technology is.  I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors.  I have a number of what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
> 
> - What are the compelling reasons to go this route?

That depends very much on your product, market, and definition process.
There are both advantages and disadvantages in SoftCPU.

+You can roll almost anything that marketing dreams up [if you can keep 
up with their changes :) ]

+Systems that need high bandwidth, sepecialised peripheral coupling can
work very well in soft-cpu

+SoftCPUs cover a very wide range: Some of the tiny ones, can run from 
block ram, and can be very good INIT and handshake problem solvers.

-You will quite often need "next size" FPGA to include the CPU.
[The FPGA vendors love this feature.. ]

-It is not actually a single chip solution : You need the loader PROM,
and some form of code execution memory. That can mean wide.high speed
data busses, and many EMC issues.
It is also not trivial to select and source that execution memory.
Again, you can "next size" the FPGA, to get enough Block Ram to run
all code on chip.

-Power consumption can take quite a hit. Static Icc on newest FPGAs is 
terrible, when compared with Std Microcontrollers.


You can, of course, have more than one controller in a design.

You might use a small uC for WDOG, Init, ADC, BrownOut, and power save 
tasks, and a larger SoftCPU, or choose one of the new larger FLASH uC,
and load the (now smaller) FPGA from that.

For uC <-> FPGA interface you can choose parallel, or the newer faster 
serial interfaces.


> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?

This is what I'd call mature technology.
Field reliability is another area in itself...

> - How much longer will it take to do it this way compared to the "old"
> way of using a separate processor and FPGA?
> 
> Then I have small picture questions like:
> 
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?

Very well, if the peripheral mix is outside the typical uC.
If you want 64 PWM channels, or special serials etc.

Just don't try and add ADCs as peripherals, or 32KHz clock
oscillators, or Brownout detectors..... :)

-jg

0
Reply Jim 4/12/2005 7:24:01 PM

Antti Lukats wrote:
> "Steve" <smkraft@pacbell.net> schrieb im Newsbeitrag
> news:1113327700.042531.314340@l41g2000cwc.googlegroups.com...
> 
>>I am looking for some information about how "real" this soft CPU
>>technology is.  I'm working with someone who has become enamored with
>>the "soft CPU" concept from the FPGA vendors.  I have a number of what
>>seem to me to be "gotta know" questions about this technology, and I
>>don't know how to get them answered. There are big picture questions
>>like:
>>
>>- What are the compelling reasons to go this route?
> 
> 
> 1) no obsolence
> 2) build your system with the peripherals and functions you need
> 3) design hardware after its has been manufactured to speed up time to
> market, the hardware is only bitstream and can be updated softly, also you
> can rework early design errors without the PCB changes
> 4) flexibility, design to be future safe, new hardware features can be added
> after product hardware is manufactured
> 5) etc..

As a practical matter, don't all of these points also apply to an 
external uC with an FPGA as a peripheral? Also, I'm a little perplexed 
by point 1 - no obsolescence  - don't FPGAs families become obsolete 
just like anything else? Or do you mean something else?

-Jeff
0
Reply Jeff 4/13/2005 2:37:00 AM

Jeff Cunningham wrote:
> Antti Lukats wrote:
> 
>> "Steve" <smkraft@pacbell.net> schrieb im Newsbeitrag
>> news:1113327700.042531.314340@l41g2000cwc.googlegroups.com...
>>
>>> I am looking for some information about how "real" this soft CPU
>>> technology is.  I'm working with someone who has become enamored with
>>> the "soft CPU" concept from the FPGA vendors.  I have a number of what
>>> seem to me to be "gotta know" questions about this technology, and I
>>> don't know how to get them answered. There are big picture questions
>>> like:
>>>
>>> - What are the compelling reasons to go this route?
>>
>>
>>
>> 1) no obsolence
>> 2) build your system with the peripherals and functions you need
>> 3) design hardware after its has been manufactured to speed up time to
>> market, the hardware is only bitstream and can be updated softly, also 
>> you
>> can rework early design errors without the PCB changes
>> 4) flexibility, design to be future safe, new hardware features can be 
>> added
>> after product hardware is manufactured
>> 5) etc..
> 
> 
> As a practical matter, don't all of these points also apply to an 
> external uC with an FPGA as a peripheral? Also, I'm a little perplexed 
> by point 1 - no obsolescence  - don't FPGAs families become obsolete 
> just like anything else? Or do you mean something else?

I think the point here is that it gives high confidence that today's 
soft CPU design, targeted to say a Spartan3, will still be able to be 
synthesised into a spartan10, XX years down the track.

In contrast, developing a product with a fixed silicon embedded 
processor + peripheral set - if it just so happens that you choose a 
CPU+peripheral combo that doesn't sell so well, there's every likelihood 
it will be end-of-lifed before too long.

Remembering of course that you don't just buy "a coldfire" (or an 8051, 
or whatever), but rather devices in this space are bundled with various 
options on the silicon - the number of combinations is finite, and you 
are at the mercy of the silicon providor to continue supplying *that 
specific combo* into the future.  FPGAs being generic means that you can 
be sure to implement the same digital system (eg CPU + peripheral combo) 
for as long as you want.

John






> 
> -Jeff
0
Reply John 4/13/2005 3:22:15 AM

>>>I am looking for some information about how "real" this soft CPU
>>>technology is.  I'm working with someone who has become enamored with
>>>
>>>- What are the compelling reasons to go this route?
>>
>> 1) no obsolence
>> 2) build your system with the peripherals and functions you need
>> 3) design hardware after its has been manufactured to speed up time to
>> market, the hardware is only bitstream and can be updated softly, also 
>> you
>> can rework early design errors without the PCB changes
>> 4) flexibility, design to be future safe, new hardware features can be 
>> added
>> after product hardware is manufactured
>> 5) etc..
>
> As a practical matter, don't all of these points also apply to an external 
> uC with an FPGA as a peripheral? Also, I'm a little perplexed by point 1 - 
> no obsolescence  - don't FPGAs families become obsolete just like anything 
> else? Or do you mean something else?
>
> -Jeff

- Most FPGAs run in high-volume, uCs often have a lot of drivates, the ones 
that are not selling well are often canceled.
- If the FPGA is finally obselete, it will be pretty easy to change the 
design to a newer product, at least if you have the VHDL-source of the core.
- In a way you are also right that this is a marketing argument, especially 
if you have no source-code. You could e.g. say, that "Nios I" is already 
obsolete, i.e. no longer good supported...

I think two further important advantages of soft-cores are:
5) reduced board-space
6) reduced costs (if the design is right. if it is not, you can run into 
additional costs by the need of a larger FPGA.)

Thomas

www.entner-electronics.com


0
Reply Thomas 4/13/2005 12:47:42 PM
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