General question about soft CPUs

I am looking for some information about how "real" this soft CPU
technology is.  I'm working with someone who has become enamored with
the "soft CPU" concept from the FPGA vendors.  I have a number of what
seem to me to be "gotta know" questions about this technology, and I
don't know how to get them answered. There are big picture questions
like:

- What are the compelling reasons to go this route?
- If we take this path, can it be made to *really* work, i.e. never
fail from one in a billion type errors?
- How much longer will it take to do it this way compared to the "old"
way of using a separate processor and FPGA?

Then I have small picture questions like:

- If you need to add peripherals (like UARTs, PWM contoller,
etc., etc.) how well does this work?
- Is the whole development environment reasonable?

I looked around on the web, and there sure is a lot of marketing
material, especially from Xilinx and Altera, but that's not what I'm
looking for.  Do you know anywhere I could get a description of how a
real commercial project has gone for somebody, so that I can get some
of my questions answered?

Thanks!
Steve

0
smkraft (1)
4/12/2005 5:41:40 PM
comp.arch.fpga 18521 articles. 20 followers. Post Follow

7 Replies
195 Views

Similar Articles

[PageSpeed] 19
Hi Steve,

    The Nios Community Forum can provide you answers to your question
on the Nios II, Nios processors, their associated development
environment, tool chain support, RTOS's and peripherals from Altera
Corp. You can access it at www.niosforum.org.

Hope this helps.

Subroto Datta
Altera Corp.

Steve wrote:
> I am looking for some information about how "real" this soft CPU
> technology is.  I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors.  I have a number of
what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
>
> - What are the compelling reasons to go this route?
> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?
> - How much longer will it take to do it this way compared to the
"old"
> way of using a separate processor and FPGA?
>
> Then I have small picture questions like:
>
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?
> - Is the whole development environment reasonable?
>
> I looked around on the web, and there sure is a lot of marketing
> material, especially from Xilinx and Altera, but that's not what I'm
> looking for.  Do you know anywhere I could get a description of how a
> real commercial project has gone for somebody, so that I can get some
> of my questions answered?
> 
> Thanks!
> Steve

0
Subroto
4/12/2005 5:48:47 PM
"Steve" <smkraft@pacbell.net> schrieb im Newsbeitrag
news:1113327700.042531.314340@l41g2000cwc.googlegroups.com...
> I am looking for some information about how "real" this soft CPU
> technology is.  I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors.  I have a number of what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
>
> - What are the compelling reasons to go this route?

1) no obsolence
2) build your system with the peripherals and functions you need
3) design hardware after its has been manufactured to speed up time to
market, the hardware is only bitstream and can be updated softly, also you
can rework early design errors without the PCB changes
4) flexibility, design to be future safe, new hardware features can be added
after product hardware is manufactured
5) etc..

> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?
almost nothing is failsafe, and extenal CPU and FPGA are possible evenso
likely to fail

> - How much longer will it take to do it this way compared to the "old"
> way of using a separate processor and FPGA?

not longer, but how much faster would be appropriate.
get some Eval board for either NIOS-II or EDK, and you are writing normal C
programs as soon as you the board and installed software

> Then I have small picture questions like:
>
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?

a few mouse clicks. the environment builds the C include files and libraries
for you

> - Is the whole development environment reasonable?

depends on your understanding of reasonable :)
yes its ready and useable, but one could wish more..

> I looked around on the web, and there sure is a lot of marketing
> material, especially from Xilinx and Altera, but that's not what I'm
> looking for.  Do you know anywhere I could get a description of how a
> real commercial project has gone for somebody, so that I can get some
> of my questions answered?
>
> Thanks!
> Steve
>

there are quite a many commercial products aroung actually I think, but
there is no list of them.

I started with new job at www.eubus.net Jan 2005, and after that Microblaze
has been used in two different redesigns (both defenetly commercial
products), besides those
http://www.hydraxc.com
is full product line totally oriented to the use of SoftCore CPU's

even though there are may be not so many references to the commercial use of
soft to core CPUs yet I am very positive that they are used more widely as
you may guess (from what is visible and public), I think the FPGA vendors
actually have some feadback about how many FPGA designs use softcore CPUs,
and this % is gorwing FAST, very FAST.

Antti














0
Antti
4/12/2005 5:55:15 PM
Steve wrote:
> I am looking for some information about how "real" this soft CPU
> technology is.  I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors.  I have a number of
what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
>

As real as anything else one might want to put into an FPGA.

> - What are the compelling reasons to go this route?

There are some reasons that drive this, depending on developer though

Control, previuosly I used ARM7TDMI external, as the FPGA got more
capability & did more work, the system was stuck with same external cpu
that was starting to become a bottleneck. Soft core cpus allow for the
EE to get control of the system and insert cpu power where it's needed
rather than depending on the ASIC supplier to help out. The worlds
greatest cpu isn't much use on the ouitside if you want it inside for
fine grain control. Some cpus are so tiny (PicoBlaze) they are hardly
recognizeable to a manager, but they may be perfectly fine for doing
some odd job FSMs. More interesting soft cpus may be just as capable as
many external cpus (<< 200MHz that is), but you get some options that
aren't possible on the outside. You could hide the soft cpu deeply, not
mention it it to marketing or the competition, and the binary that runs
on it can be merged into the FPGA bitfile, both the design, the start
up code and initial data.

Downsides include less well developed tools but thats improving with
the gcc kit being everywhere, less big companies to hold hands, less
training etc.

Also the game has really just started, as FPGAs replace ASICs, I think
we will see less opportunites for MIPs/ARM the traditional embedded
suppliers. PPC though gets it both ways since it can be an external
part or available as internal hard core for Xilinx (and to a lesser
extent ARM with Altera).

Upside usually no serious licence fee, you may even get permission to
ASIC if you want for a smidgeon compared to dealing with ARM.

Some other possibilities also include customizing the instruction set
with new opcodes that might have a huge performance boost over doing it
purely in SW even in an external much faster cpu. Or do same with a bit
more distance hook up your engines to cpu ports or links or busses.

There will come a time when people will think nothing of it and why
should the cpu be on the outside with so little access to the
internals. But there may still be use for an external cpu to hook up
with other system components.

> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?
> - How much longer will it take to do it this way compared to the
"old"
> way of using a separate processor and FPGA?
>

If you forbid the use of soft core cpus, some projects may well take
longer if thats what they need.

> Then I have small picture questions like:
>
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?
> - Is the whole development environment reasonable?
>
> I looked around on the web, and there sure is a lot of marketing
> material, especially from Xilinx and Altera, but that's not what I'm
> looking for.  Do you know anywhere I could get a description of how a
> real commercial project has gone for somebody, so that I can get some
> of my questions answered?
>
> Thanks!
> Steve


just my opinions

regards

johnjakson at usa dot com
transputer2 at yahoo dot com

0
JJ
4/12/2005 7:23:03 PM
Steve wrote:

> I am looking for some information about how "real" this soft CPU
> technology is.  I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors.  I have a number of what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
> 
> - What are the compelling reasons to go this route?

That depends very much on your product, market, and definition process.
There are both advantages and disadvantages in SoftCPU.

+You can roll almost anything that marketing dreams up [if you can keep 
up with their changes :) ]

+Systems that need high bandwidth, sepecialised peripheral coupling can
work very well in soft-cpu

+SoftCPUs cover a very wide range: Some of the tiny ones, can run from 
block ram, and can be very good INIT and handshake problem solvers.

-You will quite often need "next size" FPGA to include the CPU.
[The FPGA vendors love this feature.. ]

-It is not actually a single chip solution : You need the loader PROM,
and some form of code execution memory. That can mean wide.high speed
data busses, and many EMC issues.
It is also not trivial to select and source that execution memory.
Again, you can "next size" the FPGA, to get enough Block Ram to run
all code on chip.

-Power consumption can take quite a hit. Static Icc on newest FPGAs is 
terrible, when compared with Std Microcontrollers.


You can, of course, have more than one controller in a design.

You might use a small uC for WDOG, Init, ADC, BrownOut, and power save 
tasks, and a larger SoftCPU, or choose one of the new larger FLASH uC,
and load the (now smaller) FPGA from that.

For uC <-> FPGA interface you can choose parallel, or the newer faster 
serial interfaces.


> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?

This is what I'd call mature technology.
Field reliability is another area in itself...

> - How much longer will it take to do it this way compared to the "old"
> way of using a separate processor and FPGA?
> 
> Then I have small picture questions like:
> 
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?

Very well, if the peripheral mix is outside the typical uC.
If you want 64 PWM channels, or special serials etc.

Just don't try and add ADCs as peripherals, or 32KHz clock
oscillators, or Brownout detectors..... :)

-jg

0
Jim
4/12/2005 7:24:01 PM
Antti Lukats wrote:
> "Steve" <smkraft@pacbell.net> schrieb im Newsbeitrag
> news:1113327700.042531.314340@l41g2000cwc.googlegroups.com...
> 
>>I am looking for some information about how "real" this soft CPU
>>technology is.  I'm working with someone who has become enamored with
>>the "soft CPU" concept from the FPGA vendors.  I have a number of what
>>seem to me to be "gotta know" questions about this technology, and I
>>don't know how to get them answered. There are big picture questions
>>like:
>>
>>- What are the compelling reasons to go this route?
> 
> 
> 1) no obsolence
> 2) build your system with the peripherals and functions you need
> 3) design hardware after its has been manufactured to speed up time to
> market, the hardware is only bitstream and can be updated softly, also you
> can rework early design errors without the PCB changes
> 4) flexibility, design to be future safe, new hardware features can be added
> after product hardware is manufactured
> 5) etc..

As a practical matter, don't all of these points also apply to an 
external uC with an FPGA as a peripheral? Also, I'm a little perplexed 
by point 1 - no obsolescence  - don't FPGAs families become obsolete 
just like anything else? Or do you mean something else?

-Jeff
0
Jeff
4/13/2005 2:37:00 AM
Jeff Cunningham wrote:
> Antti Lukats wrote:
> 
>> "Steve" <smkraft@pacbell.net> schrieb im Newsbeitrag
>> news:1113327700.042531.314340@l41g2000cwc.googlegroups.com...
>>
>>> I am looking for some information about how "real" this soft CPU
>>> technology is.  I'm working with someone who has become enamored with
>>> the "soft CPU" concept from the FPGA vendors.  I have a number of what
>>> seem to me to be "gotta know" questions about this technology, and I
>>> don't know how to get them answered. There are big picture questions
>>> like:
>>>
>>> - What are the compelling reasons to go this route?
>>
>>
>>
>> 1) no obsolence
>> 2) build your system with the peripherals and functions you need
>> 3) design hardware after its has been manufactured to speed up time to
>> market, the hardware is only bitstream and can be updated softly, also 
>> you
>> can rework early design errors without the PCB changes
>> 4) flexibility, design to be future safe, new hardware features can be 
>> added
>> after product hardware is manufactured
>> 5) etc..
> 
> 
> As a practical matter, don't all of these points also apply to an 
> external uC with an FPGA as a peripheral? Also, I'm a little perplexed 
> by point 1 - no obsolescence  - don't FPGAs families become obsolete 
> just like anything else? Or do you mean something else?

I think the point here is that it gives high confidence that today's 
soft CPU design, targeted to say a Spartan3, will still be able to be 
synthesised into a spartan10, XX years down the track.

In contrast, developing a product with a fixed silicon embedded 
processor + peripheral set - if it just so happens that you choose a 
CPU+peripheral combo that doesn't sell so well, there's every likelihood 
it will be end-of-lifed before too long.

Remembering of course that you don't just buy "a coldfire" (or an 8051, 
or whatever), but rather devices in this space are bundled with various 
options on the silicon - the number of combinations is finite, and you 
are at the mercy of the silicon providor to continue supplying *that 
specific combo* into the future.  FPGAs being generic means that you can 
be sure to implement the same digital system (eg CPU + peripheral combo) 
for as long as you want.

John






> 
> -Jeff
0
John
4/13/2005 3:22:15 AM
>>>I am looking for some information about how "real" this soft CPU
>>>technology is.  I'm working with someone who has become enamored with
>>>
>>>- What are the compelling reasons to go this route?
>>
>> 1) no obsolence
>> 2) build your system with the peripherals and functions you need
>> 3) design hardware after its has been manufactured to speed up time to
>> market, the hardware is only bitstream and can be updated softly, also 
>> you
>> can rework early design errors without the PCB changes
>> 4) flexibility, design to be future safe, new hardware features can be 
>> added
>> after product hardware is manufactured
>> 5) etc..
>
> As a practical matter, don't all of these points also apply to an external 
> uC with an FPGA as a peripheral? Also, I'm a little perplexed by point 1 - 
> no obsolescence  - don't FPGAs families become obsolete just like anything 
> else? Or do you mean something else?
>
> -Jeff

- Most FPGAs run in high-volume, uCs often have a lot of drivates, the ones 
that are not selling well are often canceled.
- If the FPGA is finally obselete, it will be pretty easy to change the 
design to a newer product, at least if you have the VHDL-source of the core.
- In a way you are also right that this is a marketing argument, especially 
if you have no source-code. You could e.g. say, that "Nios I" is already 
obsolete, i.e. no longer good supported...

I think two further important advantages of soft-cores are:
5) reduced board-space
6) reduced costs (if the design is right. if it is not, you can run into 
additional costs by the need of a larger FPGA.)

Thomas

www.entner-electronics.com


0
Thomas
4/13/2005 12:47:42 PM
Reply:
Similar Artilces:

Eric Meyer on CSS question
Hi, This line is straight from page 82 of "Eric Meyer on CSS": td#main {background: #FFD; color: black; border: 2px solid #797; border-width: 2px 2px 2px 1px; } Isn't it redundant to have "2px" in the border rule when you have an explicit border-width rule? What am I missing? Jamie On Fri, 23 Jul 2004, Jamie wrote: > td#main {background: #FFD; color: black; border: 2px solid #797; > border-width: 2px 2px 2px 1px; } > > Isn't it redundant to have "2px" in the border rule when you have an > explicit border-width rule...

OS X defragging in general (Solution)
Aha! - At long last I found a solution for my install problems :) I will detail the "fix" later in this post. Background - (skip all this if you want to see the "fix") ***************************************** I posted previously: > Recently I had reason to suspect that defragging OSX might be > worthwhile under certain conditions. I had problems installing OS X version 10.3.7 from scratch. Because of a slow dialup connection, I always downloaded the individual upgrades from Apple: 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 ....and kept tho...

Using the Xilinx JTAG Interface as a General-Purpose Communication Port
For anyone interested in using the Xilinx JTAG Interface as a General-Purpose Communication Port see http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm and also http://www.s3group.com/design_expertise/fpga/gnat/ for an example (as is) design for the Spartan-3 Starter Kit Regards Bob "bob allen" <bob.allen@s3group.com> schrieb im Newsbeitrag news:d2elp8$urq$1@reader01.news.esat.net... > For anyone interested in using the Xilinx JTAG Interface as a General-Purpose Communication Port see > http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag...

Formmail Question 20406
Hi all, Newbie question about formmail program here... I want to use formmail on my contact us form, which has all the normal fields, name, address and things like that. I want to check that the names and emails fields are properly filled out when they click submit. I have the functions working but how can I run both the functions and process the form when the users click on submit button? I am thinking, can I call formmail from inside the function instead of the action? Thanks Deep Deepster wrote: > are properly filled out when they click submit. I have the functions > working but...

Raw String Question
I'm an experienced Perl developer learning Python, but I seem to be missing something about raw strings. Here's a transcript of a Python shell session: Python 3.0 (r30:67507, Dec 3 2008, 20:14:27) [MSC v.1500 32 bit (Intel)] on win32 Type "copyright", "credits" or "license()" for more information. **************************************************************** Personal firewall software may warn about the connection IDLE makes to its subprocess using this computer's internal loopback interface. This connection is not ...

Does Generals cheat in skirmishes?
I know past versions of Red Alert used to cheat eg starting with more cash building multiple buildings at once and building without the prerequisites but does Generals cheat as well? I just started playing it yesterday on hard and the computer was chineese and I had just constructed a power station, barracks, supply, war factory and two gun things and had no units. This was all done as fast as possible. Then bout 20 enemy men came walking in followed by three vehicles full of about another 30 men. I can't see the computer had the time or money to mount such an attack so early...

J2ME Memory Image Source & Serial port question
Hello there, I'm quite new to J2ME and want to try some serial port and graphics programming on my mobile (Sony Ericsson T610). So here are the questions... 1) Is there a special newsgroup for j2me programming ? 2) Is there something like a 'Memory image source' like in 'normal' desktop java applets or any other way to access a graphics frame buffer more directly than the usuall graphics commands ? 3) Can I communicate with other RS232 devices (e.g. measurement devices ?) What's the API for this ? Thanx for your help in advance ! Yours, = Michael ...

browser question
Hi there, Is there a way to prevent the browser to download or for the user to save an image from a web page? In other words the user should just see the picture on the web page without being able to save it. Thanks a lot, Calin On Mon, 13 Dec 2004, Tester wrote: > Hi there, > Is there a way to prevent the browser to download or for the user to save an > image from a web page? In other words the user should just see the picture > on the web page without being able to save it. > Thanks a lot, Calin No. The user can't see anything without his browser dow...

Re: Question on proc sql #12 648239
1. I agree with all of David's points. 2. If you wish to disregard all of the concerns, and you are willing to evaluate a complete cartesian product, consider this technique: proc sql noprint; %let ngroups = 4; select count(*) into : pop from sashelp.class; create table heightranks as select distinct class.*, count(*) as heightrank, ceil(calculated heightrank / ceil(&pop/&ngroups) ) as group from sashelp.class as class, sashelp.class as cross where class.height>=cross.height group by class.name order by heightrank; ...

Question regarding CLI array Insert
Hello, Environment: db2 V8 FP 13 LUW Our application currently uses: insert into table values ('A'),('B'),...('Z') We have used CLI arrays inserts (1000 array and commit size) and managed to insert 1 Million rows into an empty table in 32 seconds. Our current model took exactly 270 seconds. In average, the application will insert 50-100 rows at a time. There are some cases that up to 5k rows may be inserted. Multiple applications insert data into the same table concurrently. In regards to concurrency, should I expect a performance impact using CLI...

DAEMON_OPTIONS question
Hi. The documentation says: To listen on both IPv4 and IPv6 interfaces, use DAEMON_OPTIONS(`Name=MTA-v4, Family=inet') DAEMON_OPTIONS(`Name=MTA-v6, Family=inet6') but what is the default if neither is used? I assume both inet and inet6 will still be available but I want to make sure. Anyone? ~ PM ...

General Rant, Not about Lion.
i hate computers. The Principle reason that i hate computers, Is that they are Not on my side. They are constantly working against my best interests, And for no Good Reason. Why; For example, whenever i print something, The printer and Computer conspire to cut off the bottom inch of The document? Why would i EVER want to print a page of a document so that the bottom inch is missing? ? Why? Why does it cut off margins at all? Why doesn=92t it default by printing the entire page? Why would i EVER want to sacrifice content over =91format=92 ? And If i do very much want to print an entire page,...

Possible precision issue with gaming in general.
Hello, Perhaps there is a possible precision issue with gaming in general, but I am not sure. The mouse cursor moves with pixels per inch. If the screen resolution is doubled from 800x600 to 1600x1200 then the precision with which quakers would shoot is double as precise. If the resolution is switched back then it's twice as worse as it was in high resolution. However the mouse resolution is still the same, so one could argue that this is an unfair and unnecessary adventage for gamers with higher resolution monitors. Also it creates a little problem for gamers s...

Question about mathematics modelling on measured data. #2
Hi all, I am looking for a way to convert my measured data into a math model. I've measured the energy output against light incident angle on a solar panel. Therefore, I have two explanatory variables as the angle of incident light horizontally and vertically. Also, the dependent variable as energy output. I've used matlab to draw my data and it looks like a 3D bell shape graph. My next step is trying to formulate these measure data in order to perform optimization. Does anyone has some idea what and how should I do? The following link are containing my excel file and ...

questions~
I am trying a program to read some details but I have some questions. I cap 2 pics here. A trace file as below illustrates a FTP login process. The FTP host is 10.1.0.1 and the FTP server is 10.1.0.99 . How can I know the two IP hosts are on the same network? http://noripho.hp.infoseek.co.jp/ftp.gif Belows trace file shows the details of Packet #3 of ftp.gif. How can I know the remaining lifetime of this packet and how much data in bytes follows the IP header? Can this packet be fragmented if necessary? Is it a TCP protocol follows the IP header? http://noripho.hp.infoseek.co....

Generalizations
I hope it is ok to ask this here. Im having trouble with ERD's. I have been given a definition on which to draw an ERD. I did so, and began transforming the entities and relationships to relations using the following steps Step 1) Transform entities Step 2) Transform weak entities Step 3) Transform Relationships Step 4) Transform Generalizations Step 5) Simplify. When I came upon step 4 I realised I had two opportunities to generalize. A Doctor and a Patient (Both with SSN as their primary keys) could both be specializations of a 'People' entity. Likewise Pharma...

Hard drive question
Does anyone know if there is a way to read an Amiga formatted hard drive on a mac under OS9 or OSX? Thanx. -- Rob Depew http://www.geocities.com/lwanmtr http://home.earthlink.net/~lwanmtr lwanmtr@yahoo.com, lwanmtr@earthlink.net AIM:thylaknoll ICQ:165284288 In article <3FF728A3.80008@yahoo.com>, Lwanmtr <lwanmtr@yahoo.com> wrote: >Does anyone know if there is a way to read an Amiga formatted >hard drive on a mac under OS9 or OSX? A quick web search suggests that the partition table should be readable, so if you plug it in you'll probably be able to see the partitio...

tech question about souncards
the soundcard AD1986 SoundMAX on its website (http://www.analog.com/en/prod/0,2877,AD1986,00.html) is said to work on Intel, Via, SiS, ATI, nVIDIA, and ALI chipsets; which chipsets are they talking about? the motherboard one? On 9 Jun 2006 16:35:34 -0700, "heavytull" <heavytull@hotmail.com> wrote: >the soundcard AD1986 SoundMAX on its website >(http://www.analog.com/en/prod/0,2877,AD1986,00.html) is said to work >on Intel, Via, SiS, ATI, nVIDIA, and ALI chipsets; >which chipsets are they talking about? the motherboard one? It's only an AC'97 CODEC chip, ...

Lurker w/9577(s) and ebay question
Long ago I was given a 9577 that I got working. (Use Google Groups and search for "cigarette boxes 9577" if you really want to read about it.) The cd-rom died recently and I went on ebay to find one. I won item #5246083243. I used his shipping calculator link to find that $8.63 was the cost of UPS shipping to 73118. I thought that my total cost would be shipping ($8.63) + bid ($0.99), or $9.62. I assumed the shipping would be calculated correctly since I sent him a request for total price with a comment that I would prefer UPS and the calculator page includes the line:...

Xilinx timing constraint question #3
I'm using a Xilinx V2Pro part with the 6.2.03i s/w release and I'm seeing the following unconstrained path in the timing report. ================================================================================ Timing constraint: Unconstrained period analysis for net "clk_conv" Delay: 3.073ns (data path - clock path skew + uncertainty) Source: u0clk_trig_if/trig_conv0 (FF) Destination: u0clk_trig_if/trig_conv1 (FF) Data Path Delay: 3.073ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: clk_conv...

Generalization of Neural Network
Either early stopping or Bayesian regularization method is used to improve the generaliztion of the neural network. However, is it feasible to combine both of them into the neural network as the program shown below? The training funtion 'trainbr' is used for early stopping. Is it feasible? clear all;close all p = [-1:.05:1]; ptest = [-1.05:0.05:1.05]; t = sin(2*pi*p)+0.1*randn(size(p)); ttest = sin(2*pi*ptest); figure(1) subplot(2,1,1) plot(p,t,'x') hold on subplot(2,1,2) plot(ptest,ttest,'rx'); hold on val.P = ptest; val.T = ttest; net=newff([-1 1.05],[20,1],{'t...

Adapter for car/airplane question
I'm looking at the various adapters available to power notebooks on an airplane, and noticed that airplanes have a unique plug. After researching the various models, I've noticed several solutions: 1) A dedicated voltage adapter with both a cigarette lighter adapter and the airplane-specific plug. Regulates to provide no more than 72W from the airplane-specific plug due to regulations. 2) A DC-to-AC converter specifically for laptops, comes with both a cigarette lighter adapter and the airplane specific plug. Usually rated for 90W. Either of these can be had for about $50. But what ...

Good News Mr 142.179.22.210 flood microsoft.public.dotnet.general #3
Cox and Telus will not act unless they have a police file number so you may as well flood microsoft.public.dotnet.general my home Usenet group. have a nice day.Me I am nearing about TrueCrype -- Everyone leave home if Ayman's breath isn't superior. -- Michael Yardley ...

Generalizing Mixins... c++'03
Hi All, I've recently used mixins (without the courtesy of compilers supporting variadic templates) and were irritated by the fact that one had to always implement many constructors (one per base): Definition of Mixin: courtesy of http://www.drdobbs.com/cpp/184404445 A mixin is a fragment of a class that is intended to be composed with other classes or mixins... For the problem I've come up with this solution (amongst others). What do you think? ////////////////////////////////////// #include <iostream> struct Base { Base(); Base( int i, int j ){} virtual void f...

iMac G5 music CD importing question
Hi. I am the proud owner of a new iMac G5 20". I think there is a problem with the Superdrive--not sure though. When I put in a store-bought music CD, and while it is importing the tracks into iTunes, if I try to play a song on the CD that has not yet been imported (for example, the computer is importing track 3 at the moment, but I try to play track 9) the drive makes tons of noise...clicking and clacking. And eventually, it fails...meaning the iTunes freezes up, and the drive just sits there making noises. And the CD won't eject no matter what i do. I hard to restart the comput...