Hello,

I am implementing a core from xilinx (FFT) and wanted to know how the
feedback shift registers are implemented. 
The xilinx core manual says that the earlier stages that need large shift
registers uses Block RAM and other stages use distributed RAM. Does this
mean it used SRL16s?

How do the SRL16s show up in the MAP report if they are being used? Do they
show up under "Specific Feature utilization" or they are just under the
"Slices used as LUT (memory)"?

Thank you.	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Jun 25, 2:53=A0pm, "onkars"
<onkars@n_o_s_p_a_m.n_o_s_p_a_m.winlab.rutgers.edu> wrote:
> Hello,
>
> I am implementing a core from xilinx (FFT) and wanted to know how the
> feedback shift registers are implemented.
> The xilinx core manual says that the earlier stages that need large shift
> registers uses Block RAM and other stages use distributed RAM. Does this
> mean it used SRL16s?
>
> How do the SRL16s show up in the MAP report if they are being used? Do th=
ey
> show up under "Specific Feature utilization" or they are just under the
> "Slices used as LUT (memory)"?
>
> Thank you. =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com


SRL16s will be reported in the map report.  Here is a snippet from one
of mine:

  Total Number of 4 input LUTs:      24,429 out of  50,560   48%
    Number used as logic:            21,305
    Number used as a route-thru:      1,312
    Number used for Dual Port RAMs:     842
      (Two LUTs used per Dual Port RAM)
    Number used for 32x1 RAMs:          104
      (Two LUTs used per 32x1 RAM)
    Number used as Shift registers:     866

Regards,

John McCaskill
www.FasterTechnology.com