I am using Xilinx ISE 6.1 in my design on ML300 board, it's a V2P7 chip.
and in the UCF I have this line in the middle,

    Net ddr_feedback_clock   IOSTANDARD = LVCMOS25;

after this line I have a bunch of other UCF defines, and I declare
IOSTANDARD = PCI33_3 there. Towards the very end of UCF, I declare the
reset pin,

    Net sys_rst LOC=P3;

but when I run implementation, PAR error out saying on the same bank,
bank3, I am trying to use 2 IOSTANDARD, and I found that sys_rst is
somehow set to IOSTANDARD = LVCMOS25; !?

I have to specifically declare sys_rst is IOSTANDARD = PCI33_3 because
it sits at bank3 with other a banch of PCI pins.

But I wonder how come sys_rst is assigned LVCMOS25? Note that
ddr_feedback_clock is at different bank of sys_rst.

Thanks.

John Black <black@eed.com> wrote in message news:<40356AB3.B17C8147@eed.com>...
> But I wonder how come sys_rst is assigned LVCMOS25? Note that
> ddr_feedback_clock is at different bank of sys_rst.

http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0124_77.html
says:

    The default is LVTTL (except Virtex-II Pro and Virtex-II Pro X) if
no IOSTANDARD constraint is specified. The default for Virtex-II Pro
and Virtex-II Pro X is LVCMOS25.

Alan Nishioka
alann@accom.com