MapLib:978 - LUT6 symbol error during Mapping Stage

Hi, I've recently started to use the Xilinx EDK tools to create a system in whi= ch there are two AXI masters. I made these masters and then imported them u= sing the Xilinx EDK IP tool so that they would fit the AXI standard. Howeve= r when I tried compiling my design, EDK fails at the mapping stage and give= s these errors.=20 ERROR:MapLib:979 - LUT3 symbol ERROR:MapLib:979 - LUT3 symbol ERROR:MapLib:979 - LUT6 symbol ERROR:MapLib:978 - LUT3 symbol ERROR:MapLib:978 - LUT6 symbol Interestingly when I change my IP to an AXI Lite Master and comment out the= signals which are not used in AXI Lite, the design will compile. Does anyo= ne have any ideas on what may be causing this issue? and how I may be able = to resolve it? Thank you for reading my query.