More beginner's verilog questions

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After I found out that I couldn't syntesize a lot of the verilog code (
http://awlnk.com/?aRts ), I had to redesign how I was going to
implement this design.  I'm going for something significantly easier,
though I'm breaking it up into more modular parts.  I'm getting all
sorts of errors from all over the place (using both silos synthesizer
and the xilinx webpack).   The code is very simple - I want to be able
to set one of 32 pins as high, low, or high impedence using a minimal
number of input pins.  The design I came up with so far incorporates a
counter latch/demux.  I'm not sure how to implement the highimpedence
functionalty of the output, so I've ignored it for now (though I would
love some input).  Here's the code so far -- any help would be greatly
appreciated!! :

module counter32(in,reset,out);
    input [0:0] in;
    input reset;
    output [4:0] out;

	always @(posedge in) begin  /* i've seen sample code include reset
here, dont know why though */
		if (!reset)
			out = out + 1;
	end

	always @(posedge reset)
		out = 5'b00000;

endmodule

module latch32(in,out,enable,signal);
    input [5:0] in;
    output [31:0] out;
    input enable;
    input signal;
    integer N;

    always @(posedge enable)
    	out[in] = signal;

endmodule


module counterLatch32(in,reset,enable,signal,out);
    input [0:0] in;
    input [0:0] reset;
    input [0:0] enable;
    input [0:0] signal;
    output [31:0] out;

    wire [4:0] select;
    reg [31:0] out;

    module counter32(in, reset, select);
    module latch32(select, out, enable, signal);

endmodule

0
Reply google61 (5) 12/20/2005 12:40:28 AM

See related articles to this posting


I'd pick up any book on Verilog and read the first 2-3 chapters.  This will 
solve a majority of your problems.  You're making fundamental mistakes with 
the shown code.

"Reza Naima" <google@reza.net> wrote in message 
news:1135039228.101043.151430@o13g2000cwo.googlegroups.com...
> After I found out that I couldn't syntesize a lot of the verilog code (
> http://awlnk.com/?aRts ), I had to redesign how I was going to
> implement this design.  I'm going for something significantly easier,
> though I'm breaking it up into more modular parts.  I'm getting all
> sorts of errors from all over the place (using both silos synthesizer
> and the xilinx webpack).   The code is very simple - I want to be able
> to set one of 32 pins as high, low, or high impedence using a minimal
> number of input pins.  The design I came up with so far incorporates a
> counter latch/demux.  I'm not sure how to implement the highimpedence
> functionalty of the output, so I've ignored it for now (though I would
> love some input).  Here's the code so far -- any help would be greatly
> appreciated!! :
>
> module counter32(in,reset,out);
>    input [0:0] in;
>    input reset;
>    output [4:0] out;
>
> always @(posedge in) begin  /* i've seen sample code include reset
> here, dont know why though */
> if (!reset)
> out = out + 1;
> end
>
> always @(posedge reset)
> out = 5'b00000;
>
> endmodule
>
> module latch32(in,out,enable,signal);
>    input [5:0] in;
>    output [31:0] out;
>    input enable;
>    input signal;
>    integer N;
>
>    always @(posedge enable)
>    out[in] = signal;
>
> endmodule
>
>
> module counterLatch32(in,reset,enable,signal,out);
>    input [0:0] in;
>    input [0:0] reset;
>    input [0:0] enable;
>    input [0:0] signal;
>    output [31:0] out;
>
>    wire [4:0] select;
>    reg [31:0] out;
>
>    module counter32(in, reset, select);
>    module latch32(select, out, enable, signal);
>
> endmodule
> 


0
Reply Rob 12/20/2005 4:05:49 AM

I will agree with Rob, you need a book. Clearly this is a homework
problem . . but you did a good job to start. So here are some pointers
that should help.

Generally :

1. Name your ports and your I/O's, something that means something.
"in", "out", "signal" are not very helpful. All these devices should
have an input called "clk".
2. Whenever assigning a sequential element ( flop / latch ) using a
reg, use the '<=' non-blocking assignment operator in verilog. This
will save you many headaches in the future.
3. [0:0] is unecessary, as an unsized input, output, reg or wire is
always 1 bit or [0:0].

Specifically:
1. (counter32) Don't assign a value (out) from two different
always-blocks. This is a synchronous version of the same flop, with an
enable ( en ) , and a clear ( in place of reset ) .

always @(posedge clk)
  if ( !clr)
    out <= (en) ? out + 1 : out  ;
  else
    out <= 'b0 ;

2. Latches are troublesome and usually not preferred in FPGA design, if
you can use a flop. But if ( god forbid ) you need one. Here is how to
code it :

always (clk or d)
  if ( clk ) q <= d ;

This is a single bit flop. Who's value is set on the output whenever
any value changes and the clock is high ( the definition of a latch ) .


3. (counterLatch32) You are confusing module declaration with module
instantiation. A declaration using the word "module" followed by the
name of a module, followed by all the stuff in a module, followed by
the word "endmodule". What you need to do is make an instance of a
block so it might look like this :

counter32 count_a ( .clk(clk), .en(en), .reset(reset), .out(out) ) ;

This will instance a counter32 module and connect its inputs and
outputs to wires to wires of the same name in the parents module scope.
The instance name will be count_a.

I hope this all makes sense. I am sure you can find some good online
FAQ's about verilog. Please look up those for further info. Best way to
learn is by just copying someone else. 

-Art

0
Reply Art 12/20/2005 5:02:48 AM

I bought a book a book recommended by one of the application engineers
at a reseller of Xilinx  (Verilog HDL), and it described verilog very
well.  But it didn't distinguish between what was used for simulation
and what is synthesizeable.  So my first bit of code (if you look at
the link) worked fine on the simulator, but it relied heavily on
constructs that could not be synthesized.  I then asked for
recommendations on books, and was told that there were no good ones.
Hence I'm hoping I can get some pointers to reference code, or some
help debugging the code I wrote.  

Thnx,
Reza

0
Reply Reza 12/20/2005 7:34:33 AM

Art!

Thanks so much for the pointers.  I've gone through the literature (the
book I have), but it's all about syntax and nothing about practical
applicaiton.  A few quesitons however :

- why do you need a clk?  Why does anything need a clock?  If I can
synthesize a device which is a set of nested gates (i.e. an 'AND' gate)
which perform logic, where does the clock come in?
- why  out <= (en) ? out + 1 : out  ;  ?  Why not  "out <= (en) ? 1 :
out"  Though I'm more interested in "out[index] <= (en) ? in :
out[index]" -- can I do that?  i.e the counter determines the index,
and the enable alows me to latch the value.
- is it possible to have the input (in) above be tri-state, such that I
can latch 0, 1, Z? (i think Z is high-impedence)


Thanks again - I'll start playing with some of the suggested changes
and see how far I can get.  
Reza

0
Reply Reza 12/20/2005 7:44:23 AM

Reza -

Most designs use a clock becuase they are synchronous designs. Current
methodologies favor this design style for many reasons, too many to go
into here.  In a synchronous system, all logic is clocked by some
(small)
number of system clocks.  This makes timing analysis easier and avoids
a lot of potential bugs.

You should take a look at some real life examples of Verilog code to
see
how it is written in the real world.  There are lots of sources to look
at
on the web, take a look at some of the simpler designs at opencores.org

One thing to remember - some of the Verilog language can't be
synthesized.
When you're coding something, try to imagine what the hardware would
look like.  For example, the "wait()" construct is not synthesizable.
Why?
Could you imagine harware to implement something like wait()?

Good Luck!

John Providenza

0
Reply johnp 12/20/2005 4:20:52 PM

Reza Naima wrote:

> - why do you need a clk?  Why does anything need a clock?

I suggest you take a course on digital electronics design.  If you're
asking "why do you need a clock," you've got a lot of ground to cover
before you start trying to design with Verilog.

-a

0
Reply Andy 12/20/2005 5:11:27 PM

I think John answered the question by stating that the clock is useful
for syncronization and debugging, but ultimatly it seems as if I am
correct in my assertion that a clock is not explicitly required.

Digital electronics design seems a bit vague - can you be a bit more
specific?  There are verilog-specific courses offered in my program
(I'm in graduate school) - but I think it's an overkill for my needs.

Alas, the current project I'm working can't wait for me to take more
classes.  Either this is implemented in a CPLD or else I'll have to use
discrete components.  I'm going to follow some of Art's suggestions and
see how far I can get.

I've also looked at some of the sample designs on opencores, and they
seem a bit too complex to learn from.  I'll look around for some other
simpler sample code.  One of the other problems with looking at sample
code is that a lot of it is minimally commented, and it's very hard to
figure out why people are implementing someting in one way vs. another
way.

With regards to a wait(), I figured the compiler/synthesizer would
generate some sort of clock/counter with some sort of comparator to
trigger the event.  I was hoping that the synthesizers were a bit
smarter than they seem to be.  

Thanks,
Reza

0
Reply Reza 12/20/2005 8:50:41 PM

Oh, one other question regarding clocks.  By not using one, wouldn't
the device consume significantly lower power?  I still don't see an
advantage of having a clock in this design.  

Thnx,
reza

0
Reply Reza 12/20/2005 8:53:58 PM

Reza Naima wrote:
> I think John answered the question by stating that the clock is useful
> for syncronization and debugging, but ultimatly it seems as if I am
> correct in my assertion that a clock is not explicitly required.

True if your design is 100% combinational
without a single shifter or counter.

> Alas, the current project I'm working can't wait for me to take more
> classes.  Either this is implemented in a CPLD or else I'll have to use
> discrete components.

In that case, consider schematic capture to enter your design:
http://www.eecg.toronto.edu/~zvonko/AppendixB_quartus.pdf

> With regards to a wait(), I figured the compiler/synthesizer would
> generate some sort of clock/counter with some sort of comparator to
> trigger the event.  I was hoping that the synthesizers were a bit
> smarter than they seem to be.  

That seems to be a common expectation.
Unfortunately it is difficult to describe
some sort of clock/counter without a clock input.

         -- Mike Treseler
0
Reply Mike 12/20/2005 9:16:25 PM

With regards to the clock - the design has a counter, but all the
counter does is count the number of pulses that come in.  I can't see
how a seperate clock would be required for a counter.

Also, are there some sort of standars for using a clock?  Can you flag
an input as being a clock such that the synthesizer would do something
special/different with it?  Or is it just a input that you deal with in
your own way?

Thnx,
Reza

0
Reply Reza 12/21/2005 3:26:52 AM

I have used the following book and it has been very helpful.

Modeling, Synthesis, and Rapid Prototyping with the VERILOG (TM) HDL
by Michael D. Ciletti

"Reza Naima" <google@reza.net> wrote in message 
news:1135064071.868137.197590@z14g2000cwz.googlegroups.com...
>I bought a book a book recommended by one of the application engineers
> at a reseller of Xilinx  (Verilog HDL), and it described verilog very
> well.  But it didn't distinguish between what was used for simulation
> and what is synthesizeable.  So my first bit of code (if you look at
> the link) worked fine on the simulator, but it relied heavily on
> constructs that could not be synthesized.  I then asked for
> recommendations on books, and was told that there were no good ones.
> Hence I'm hoping I can get some pointers to reference code, or some
> help debugging the code I wrote.
>
> Thnx,
> Reza
> 


0
Reply Rob 12/21/2005 3:38:47 AM

Reza,
Well,What is it that you have thought of the RTL of the counter you
would like to code?

0
Reply santosh 12/21/2005 6:53:30 AM

Santosh -

I'm not sure if I understand your question, or what an RTL stands for.
Based on the feedback, I rewrote the module so it looks like this (and
is much simpler looking) :

module counterLatch32(counter_increment, in, reset, enable, out);
    input in;
    input counter_increment;
    input reset;
    input enable;
    output [31:0] out;

    reg [4:0] index;
    reg [31:0] out;

	always @(posedge counter_increment or posedge reset) begin
		if (!reset)
			index <= index + 1;
		else
			index <= 5'b00000;
	end

	always @(posedge enable)
		out[index] <= in;

endmodule

I still don't see a need for a clock - can someone shed some light into
a case where a clock would be helpful?  I'm still getting errors.  Just
this one so far....

ERROR:Xst:898 - counterlatch32.v line 12: The reset or set test
condition for <index> is incompatible with the event declaration in the
sensitivity list.


reza

0
Reply Reza 12/21/2005 12:06:29 PM

   Hmm, right now I don't see what it's complaining about, since the asynchronous reset is active 
high.  My suggestion would be to rearrange the blocks a little.  Try something like:

  	always @(posedge counter_increment or posedge reset) begin
  		if (reset)
  			index <= 5'b00000;
  		else
  			index <= index + 1;
  	end


	Am I missing something obviously wrong with the sensitivity list here?  Or is it just a problem 
with the synthesiser?


Reza Naima wrote:
> Santosh -
> 
> I'm not sure if I understand your question, or what an RTL stands for.
> Based on the feedback, I rewrote the module so it looks like this (and
> is much simpler looking) :
> 
> module counterLatch32(counter_increment, in, reset, enable, out);
>     input in;
>     input counter_increment;
>     input reset;
>     input enable;
>     output [31:0] out;
> 
>     reg [4:0] index;
>     reg [31:0] out;
> 
> 	always @(posedge counter_increment or posedge reset) begin
> 		if (!reset)
> 			index <= index + 1;
> 		else
> 			index <= 5'b00000;
> 	end
> 
> 	always @(posedge enable)
> 		out[index] <= in;
> 
> endmodule
> 
> I still don't see a need for a clock - can someone shed some light into
> a case where a clock would be helpful?  I'm still getting errors.  Just
> this one so far....
> 
> ERROR:Xst:898 - counterlatch32.v line 12: The reset or set test
> condition for <index> is incompatible with the event declaration in the
> sensitivity list.
> 
> 
> reza
> 
0
Reply Jason 12/21/2005 2:39:08 PM

I believe that you need to give XST hints to infer logic that maps onto
the architecture.  I was at a Xilinx presentation where they used the
RSE letters to denote the order of priority that operations need to
be entered in order to map onto the flip-flop efficietnly:
always @(posedge clk)
  if (Reset)
     // reset stuff 1st
  else if (Set)
    // set stuff second
  else if (Enable)
   // enabled logic last

This is because of the priority of the Reset/Set/Enable functions built
into
the flip-flops.

It could be that the original code fragment confuses the code
generator.

John P

0
Reply johnp 12/21/2005 4:07:10 PM

See the things in you design which are always @ (posedge xyzzy) begin
foo <= bar, the xyzzy is a clock, even if you don't call it clock.
The foo <= bar is an "edge clocked" flip-flop/register. Things happen
on the posedge of the xyzzy clock.  If the clock is "periodic" hooked
up to some kind of oscillator, then it is obvious that it is a
clock. However, even if the clock is not periodic, it is still a clock
and it tells "when" something happens.

Hope this helps,
-Chris

*****************************************************************************
Chris Clark                    Internet   :  compres@world.std.com
Compiler Resources, Inc.       Web Site   :  http://world.std.com/~compres  
23 Bailey Rd                   voice      :  (508) 435-5016
Berlin, MA  01503  USA         fax        :  (978) 838-0263  (24 hours)
------------------------------------------------------------------------------

0
Reply Chris 12/21/2005 4:38:26 PM

Reza Naima wrote:
> Santosh -
>
> I'm not sure if I understand your question, or what an RTL stands for.
> Based on the feedback, I rewrote the module so it looks like this (and
> is much simpler looking) :
>
> module counterLatch32(counter_increment, in, reset, enable, out);
>     input in;
>     input counter_increment;
>     input reset;
>     input enable;
>     output [31:0] out;
>
>     reg [4:0] index;
>     reg [31:0] out;
>
> 	always @(posedge counter_increment or posedge reset) begin
> 		if (!reset)
> 			index <= index + 1;
> 		else
> 			index <= 5'b00000;
> 	end
>
> 	always @(posedge enable)
> 		out[index] <= in;
>
> endmodule
>
> I still don't see a need for a clock - can someone shed some light into
> a case where a clock would be helpful?  I'm still getting errors.  Just
> this one so far....

THINK HARDWARE.  What sort of logic will this code create?

Answer: some flip-flops.  And flip-flops require a clock to change
state.  In the example you give above, the signal counter_increment is
used as the flops' clock input.  (You might want to read the synthesis
tool manual to learn why.)

The other gotcha that you probably don't realize is that the signal
enable will ALSO be used as a clock for the flips in the signal out.
On every rising edge of enable, the value of in will be clocked into
out.  Again, a simple perusal of the synthesis tool manual will explain
why.

> ERROR:Xst:898 - counterlatch32.v line 12: The reset or set test
> condition for <index> is incompatible with the event declaration in the
> sensitivity list.

That's because your code doesn't follow the templates for synthesizable
flip-flops.  Specifically, you can't do anything "more complex" than
assigning constants (the reset values) to the flops in the if (reset
....) clause.

The other reason for the error is that the asynchronous reset has
priority over the synchronous update.  You've coded it such that the
synchronous update has the higher priority.

-a

0
Reply Andy 12/21/2005 4:52:22 PM

Reza Naima wrote:
> I think John answered the question by stating that the clock is useful
> for syncronization and debugging, but ultimatly it seems as if I am
> correct in my assertion that a clock is not explicitly required.

Not knowing the details of your design makes it a bit difficult to tell
whether a global clock is necessary, but the reason for synchronous
design (the entire design clocked by a global clock) is that is
simplifes timing analysis and helps to ensure that the design will
actually work.

> Digital electronics design seems a bit vague - can you be a bit more
> specific?  There are verilog-specific courses offered in my program
> (I'm in graduate school) - but I think it's an overkill for my needs.

I'm actually talking about Digital Electronics Design 101 -- back to
basics.

> Alas, the current project I'm working can't wait for me to take more
> classes.  Either this is implemented in a CPLD or else I'll have to use
> discrete components.  I'm going to follow some of Art's suggestions and
> see how far I can get.

Can the project wait for you to develop the skills to ensure that it is
successful?

> With regards to a wait(), I figured the compiler/synthesizer would
> generate some sort of clock/counter with some sort of comparator to
> trigger the event.  I was hoping that the synthesizers were a bit
> smarter than they seem to be.

The synthesizers _are_ very smart, but you don't want them to be too
smart.  The tools are capable of generating logic that may be
functionally correct, but may be too large to fit in a chip, or may not
run at the required speed, or both.  Writing concise descriptions
allows the tools to produce a more optimal result.

-a

0
Reply Andy 12/21/2005 5:03:43 PM

>> I still don't see a need for a clock - can someone shed some light into
>> a case where a clock would be helpful?  I'm still getting errors.  Just
>> this one so far....
>>
>> ERROR:Xst:898 - counterlatch32.v line 12: The reset or set test
>> condition for <index> is incompatible with the event declaration in the
>> sensitivity list.
>>
>>
>> reza
>>

Asynchronous logic does not belong in FPGAs.  They are not designed for 
it and the tools don't support it (especially static timing analysis).
Wires in FPGAs have delays associated with them that are on the same 
order of magnitude as the delays through the logic primitives.

While your ripple count structure is a viable clock structure, it does
have some things you need to watch out for: 1), the outputs do not 
update all at once, rather the lsb changes, then the next bit and so on, 
hence the name ripple count.  As the counter gets wider, the maximum 
count speed at which you can extract a usable count diminishes (but note
that if you don't need the lower order bits, this can be faster than a
synchronous counter).  2) The input is sensitive to glitches on the 
input signal.  Mechanical switches will 'bounce', so you'll need to 
include logic to filter out the multiple switch closures that happen
every time you actuate the switch.

Timing analysis (studying the time delays in your circuit to make sure 
that it will run as fast as you need it to and that it won't break 
because of signals getting somewhere either too fast or too late) is 
much easier in a synchronous design (one where a common clock is 
distributed to all the flip-flops in the design) because each timing 
path is punctuated by the flip-flops...you only need to evaluate the 
propagation delay time from flip-flop to flip-flop.  In an async system, 
you need to take into account the propagation delays on all paths from 
the input to the output to make sure you don't have race conditions that 
would upset the proper operation of your circuit.  Also, synchronous 
design eliminates the dynamic hazards you need to deal with in an async 
design.

Even asynchronous resets are bad for FPGA design.  First, the tools 
don't trace the delay paths for the asynchronous reset through the 
flip-flop, so you could wind up with timing hazards and not be aware of 
it.  Second, there are start up hazards which have been discussed ad 
nauseum here in the past.  If you really need an async behavior, for 
whatever reason, just connect the external async reset to the PROGRAM 
pin on the FPGA.
0
Reply Ray 12/21/2005 6:17:10 PM

Before I start replying to people, I was just wondering, how is it
possible such that I can assign a high-impedence state to an output
using the code I wrote?   Can I do it using the same number of inputs,
or do I have to add another input and implement it in this way..

always @(posedge clear)
    out[index] <= z

or something like that?

Jason -

Yep, this did the trick, and managed to piss me off at the same time.
I don't see how this code is logically any different from the code that
I posted!   Several people posted about hints and priorities for
coding, but in my reading, I never came across references to these
things.  Does anyone have any good pointers or references?

Ray -

Is it acceptible to use asynchronous code in fpga's/cpld's if you are
going to be working at very low speeds?  I'm not looking for a high
performance design, rather, a super-low-power deisgn that'll save me
pins on a microcontroller.   I just want the ability to program one of
32 outputs using a minimal set of microcontroller pins.

With regards to switch bouncing, as it'll be switched from a
microcontroller, I dont have to deal with debounce, right?

Finally, I'm not sure what the reset/startup up hazards are -- I'll do
some googling after I post this.  The reset I use is just to reset the
counter to zero.  Will this be problematic?


Andy -

Thanks for  the hint about the falling edge of the enable pin.  Can you
provide me with some some pointers as to why this behaviour is the way
it is - or a starting point when I'm going through the manual.

This behaviour makes no logical sense again, just as this notion of
having to fllow templates and priorities.  Is there any benefit for
such a strict structure?  If a reset is higher in priority, why doesn't
the compiler/synthesizer just take care of it.  Why not just give me a
warning rather than a hard error.

 I also checked my course schedule, and there are not classes called
Digital Electronic Design or anything like that.  What material would
such a course cover?  Also, the project can't wait.  If it can't be
done in a CPLD, we'll have to do it using either a larger
microcontroller or discrete multiplexers/counters.  We're building an
implantable wireless neural recording device to record and transmit
data from a 32 channel probe, and the key factors are size and power
consuption (in that order).  The entire device should be no bigger than
two quarters stacked on top of each other - which is why I wanted to go
with a CPLD rather than a large microcontroller or several discrete
components.  


Thanks everyone for your help so far!
Reza

0
Reply Reza 12/21/2005 8:13:42 PM

Reza Naima wrote:
> Before I start replying to people, I was just wondering, how is it
> possible such that I can assign a high-impedence state to an output
> using the code I wrote?   Can I do it using the same number of inputs,
> or do I have to add another input and implement it in this way..
> 
> always @(posedge clear)
>     out[index] <= z
> 
> or something like that?

   I guess that depends on whether you're trying to tri-state an output pad from the FGPA itself or 
an internal node.  Are you trying to create a tri-state bus WITHIN the FPGA?  I've never tried to 
synthesize something like that but I guess you'd have to use the 'z' constant.  Never tried it.

   If you're tristating an output I'd expect a tri-state enable connection to the pad itself.  That 
will be much more tool specific.

> Yep, this did the trick, and managed to piss me off at the same time.
> I don't see how this code is logically any different from the code that
> I posted!   Several people posted about hints and priorities for
> coding, but in my reading, I never came across references to these
> things.  Does anyone have any good pointers or references?
> 

   Well, synthesis tools usually infer priority to if-else constructs.  Now, you can argue that with 
a single condition to the 'if-else' that neither block has higher priority.  But with nested trees 
of if-else's there is a definite priority.

   So the synthesizer has to map the code to cells existing in the FPGA.  With an asynchronous reset 
to a FF it's really a level sensitive input.  Anytime that the reset is asserted the output should 
be driven to the reset state.  Might not seem like a level sensitive input, but it is.  If 'posedge 
clk' occurs it should not be able to set the outputs, hence the highest priority portion of the 'if' 
structure is the comparision against the asynchronous reset.

   But the way that you had it written it had the non-reset case as the highest priority in the 
if-else statement.  I've argued in the past with people that there is NO priority for a simple two 
segment if-else since there is no nesting of branches, but it's kinda semantic.



> This behaviour makes no logical sense again, just as this notion of
> having to fllow templates and priorities.  Is there any benefit for
> such a strict structure?  If a reset is higher in priority, why doesn't
> the compiler/synthesizer just take care of it.  Why not just give me a
> warning rather than a hard error.

   One of the issues is that you're not creating new base cells.  Just mapping to existing ones.  As 
for the 'template' type aspect, it's a matter of strict logical correctness.  If it can't map the 
behaviour that you've specified to an existing cell, what else can it do?

   Also, don't forget that someone had to code the synthesizer :->
0
Reply Jason 12/21/2005 9:07:10 PM

Ray Andraka wrote:
> Asynchronous logic does not belong in FPGAs.  They are not designed
> for it and the tools don't support it (especially static timing
> analysis).

I recently needed a data path with a 56-bit adder/subtractor with binary
and BCD modes.  I thought I might have to pipeline it, but was
pleasantly surprised that the Xilinx tools did a very good job with it
as purely combinatorial logic.

The inputs come from a mux from one of five registers or a few other
sources, and the outputs can be loaded into any of four registers.  As
an additional complication, the arithmetic operation may be performed on
any subrange of four-bit digits of the 56-bit word, which means that
there is a 14:1 mux for carry out, and 2:1 muxes in the carry of each
digit.

I designed a four-bit slice using three ripple-carry adders: one to
generate the one's or nine's complement of the subtrahend, one for the
binary addition, and one for the for the BCD correction of the result.

For each digit, I use two of those slices, one with the carry-in tied
high, and one with it tied low.  The carry outs of those act as the
generate and propogate outputs for a carry lookahead scheme.  And the
data outputs feed a multiplexer selected by the carry-in computed by the
lookahead carry logic, so they act as carry-select adders.

When I set the mapper to use timing-directed mapping, and the PAR to
high effort, ISE 8.1i was able to reduce it to ten levels of logic
(including the input muxing), and static timing analysis says it will
run with under 20 ns clock cycle in an XC3S1000-4 (the slower speed
grade).

I was not expecting the tools to be able to optimize it this well,
especially as synthesis translated the carry-lookahead code, which I'd
carefully written describing very flat logic, into a thirteen-deep tree.
But apparently the mapper and PAR were smart enough to flatten it again.

The static timing analysis had to analyze an immense number of paths.
But I don't have any feedback loops in the logic, so I guess analysis of
it isn't particularly difficult, just a large combinatorial problem.

A pipelined design would probably achieve better throughput, but worse
latency, and for my purposes latency was important.  I'm not very
experienced with complex data path and arithmetic design, so perhaps
there are more efficient ways to implement a binary/BCD add/subtract
slice, but even so I don't expect that it's possible to reduce the
number of levels of logic of the purely combinatorial approach much.
0
Reply Eric 12/21/2005 10:13:34 PM

I'm trying to get a tri-state output  ([31:0] out).  Any idea how to
implement it?

Thnx,
Reza

>    I guess that depends on whether you're trying to tri-state an output pad from the FGPA itself or
> an internal node.  Are you trying to create a tri-state bus WITHIN the FPGA?  I've never tried to
> synthesize something like that but I guess you'd have to use the 'z' constant.  Never tried it.
>
>    If you're tristating an output I'd expect a tri-state enable connection to the pad itself.  That
> will be much more tool specific.
>

0
Reply Reza 12/21/2005 10:25:06 PM

Reza -

I suggest you do some studying on your own rather than asking this
group to design your circuit.

On your tri-state question, try Google "verilog tristate", then do some
reading.

John Providenza

0
Reply johnp 12/21/2005 10:46:48 PM

John,

I'm just trying to use the usenet as a resource to learn.  In reading
other sources, it seems that I could output a 'z' in order to achieve a
tri-state -- however, as I've found out, there is a lot of strange
behaviour in actually going from verilog syntax to application and
implementation.  I wanted to see if there were any gotcha's in this
approach.  I also wanted to know if it was possible for a physical
input to read 'z' if I configure the microcontroller's pin as an input
(putting it in tri-state), or if I would have to add another pin (say,
enable_Z) to specify when I want the output to be equal to 'z'.  I'm
also not sure about the implementation differences - say, between
xilinx and altera, and if one supports a certain mode of opperation
that the other does not.

I'll do some more googling on verilog and tristate, however, I also
find that there are people willing to help answer questions, which I
greatly appreciate.  I'm not asking anyone to design my circuit -
though people have helped with some of the debugging issues which has
been invaluable.

Another aspect of my questions is trying to understand the strange
behaviour.  I still don't see why the synthesizer has a problem
equating these two constructs :

If A do a else do b
If !A do b else do a

they seem identical to me, and I'll have to do some more research and
re-read some of the replies to this thread to try to figure it out.

In any case, thanks,
Reza

0
Reply Reza 12/22/2005 2:52:07 AM

Both Altera and Xilinx give the ability to look at the RTL schematic which 
will show you what the synthesizer did with your code.  I don't know if the 
free versions give you this ability????

Your question about whether or not your microprocessor can read a 'z' 
clearly tells us that you're not an engineer working in industry.

"Reza Naima" <google@reza.net> wrote in message 
news:1135219926.957661.32390@g47g2000cwa.googlegroups.com...
> John,
>
> I'm just trying to use the usenet as a resource to learn.  In reading
> other sources, it seems that I could output a 'z' in order to achieve a
> tri-state -- however, as I've found out, there is a lot of strange
> behaviour in actually going from verilog syntax to application and
> implementation.  I wanted to see if there were any gotcha's in this
> approach.  I also wanted to know if it was possible for a physical
> input to read 'z' if I configure the microcontroller's pin as an input
> (putting it in tri-state), or if I would have to add another pin (say,
> enable_Z) to specify when I want the output to be equal to 'z'.  I'm
> also not sure about the implementation differences - say, between
> xilinx and altera, and if one supports a certain mode of opperation
> that the other does not.
>
> I'll do some more googling on verilog and tristate, however, I also
> find that there are people willing to help answer questions, which I
> greatly appreciate.  I'm not asking anyone to design my circuit -
> though people have helped with some of the debugging issues which has
> been invaluable.
>
> Another aspect of my questions is trying to understand the strange
> behaviour.  I still don't see why the synthesizer has a problem
> equating these two constructs :
>
> If A do a else do b
> If !A do b else do a
>
> they seem identical to me, and I'll have to do some more research and
> re-read some of the replies to this thread to try to figure it out.
>
> In any case, thanks,
> Reza
> 


0
Reply Rob 12/22/2005 3:16:20 AM

Reza Naima wrote:

> Before I start replying to people, I was just wondering, how is it
> possible such that I can assign a high-impedence state to an output
> using the code I wrote?   Can I do it using the same number of inputs,
> or do I have to add another input and implement it in this way..
> 
> always @(posedge clear)
>     out[index] <= z
> 
> or something like that?
> 
> Jason -
> 
> Yep, this did the trick, and managed to piss me off at the same time.
> I don't see how this code is logically any different from the code that
> I posted!   Several people posted about hints and priorities for
> coding, but in my reading, I never came across references to these
> things.  Does anyone have any good pointers or references?
> 
> Ray -
> 
> Is it acceptible to use asynchronous code in fpga's/cpld's if you are
> going to be working at very low speeds?  I'm not looking for a high
> performance design, rather, a super-low-power deisgn that'll save me
> pins on a microcontroller.   I just want the ability to program one of
> 32 outputs using a minimal set of microcontroller pins.
> 
> With regards to switch bouncing, as it'll be switched from a
> microcontroller, I dont have to deal with debounce, right?
> 
> Finally, I'm not sure what the reset/startup up hazards are -- I'll do
> some googling after I post this.  The reset I use is just to reset the
> counter to zero.  Will this be problematic?
> 
> 

Generally, you should avoid async logic.  By using it, you are making 
your job a lot harder, and substantially increasing the risk of making a 
grave design error that may not show up until the device is fielded. 
Yes, asynchronous designs are possible in FPGAs and CPLDs, but it takes 
a considerable amount of additional design evaluation and verification 
effort to make sure you did it right.  Often times, it also involves 
hand routing to maintain control of the path delays, and it certainly 
includes timing analysis by hand because the static timing tools are not 
suited to async circuit evaluation.  I would certainly strongly 
discourage someone who is having trouble understanding the advantages of 
a synchronous design taking an asynchronous approach to the design.

The issue is not the speed of the design, it is the numerous hazards 
present in an async design that are eliminated by synchronous design 
techniques.  The fact that the wires connecting the elements have delay 
in an FPGA and that delay varies significantly for each routing solution 
makes the analysis of an async design in an FPGA extremely tedious, 
error prone, and difficult.  As soon as you have to make a modification 
to the design, you basically have to start over on the analysis. If you 
don't have time to learn how to do a basic synchronous design, you don't 
have the time to do the async design properly either.

The reset/start up hazards in a synchronous design with async reset is 
that unless the release of reset is done synchronously, you can't 
guarantee that all affected logic is going to see the release of reset 
on the same clock cycle, so it can wind up leaving the reset state in an 
unknown condition.  Your reset to zero is OK as long as you can 
guarantee all of the counter flip-flops will not be clocked until the 
set-up times to all the flip-flops have been satisfied.

Finally, an FPGA or CPLD is generally NOT suitable for an implantable 
device.  Even the static current greatly exceeds the current draw needed 
for a reasonable battery life, regardless of what the dynamic currents 
are in your design.  The FPGA or CPLD is fine for a prototype, but not 
for the actual implant.  Finally, if speed is not a consideration and 
power is, there is no reason you can't make the design synchronous and 
slow the clock down to the minimum clock you need.  A 32KHz digital 
watch crystal will provide a dynamic power that is barely detectable 
over the static ICC in most FPGAs and CPLDs.  Also, the power savings 
for an async design in and FPGA is largely a mirage. By using 
synchronous techniques you take advantage of purpose built structures in 
the FPGA such as the optimized clock tree and fast logic for carry 
chains, and other arithmetic.  Async logic often has to use LUT 
resources and general purpose routing instead, and because the routing 
is actually a network of powered switches, the power dissipation is 
quite a bit higher than you might expect.  Also, there have been papers 
showing that a heavily pipelined (ie very little logic between 
flip-flops) design shows significant power reductions (on the order of 
20-30%) over the same design with fewer pipeline stages. The difference 
is the flip-flops stop the propagation of glitches, which in turn 
dissipates a significant amount of power not only in the logic but also 
in the active routing resources.

I strongly encourage you to take a bit of time to learn synchronous 
design.  I'd pick up a basic logic text such as Morris Mano and start 
reading up on synchronous logic.
0
Reply Ray 12/22/2005 4:27:41 AM

Rob,

I never asked if a microprocessor could read a 'z', I asked if a CPLD
could determine if an input was floating or not - though I doubt it
could.  And as I've stated, I'm a graduate student, so I'm obviously
not working in industry.  I take it you like to skim.

I found the RTL schematic viewer - though I sitll am not sure what RTL
stands for.   

Reza

0
Reply Reza 12/22/2005 9:03:23 AM

Ray,

Thanks for the excellent advice and help.  A few comments/responses.

- The implant is actually inductivly powered through the skin and there
is no battery.  For the xlinix chips I was looking at, quiesent power
consuption was under 30uA which is perfectly fine.  We're looking at
having about 50-100mA @ 3.3v available to use for all components (amp,
a2d, uC, cpld, telemetry system).

- The async verilog code will only be run once every few days, and will
be controlled from a microcontroller that I can tweak to guarantee
sufficient time between each state change.  I do have a clock available
that I could feed into it to make it a synchronous design - but I'll go
for the async first to see if I can get it to work.

- I'll look into finding a copy of Morris Mano's book.

Thanks,
Reza

p.s. I've added some extra code (see below) that is synthesized just
fine on one of the xilinx CPLDs, but gives errors if I configure it for
another CPLD types.  It says it can't find a matching template for the
other cpld architectures.   I also found that I had to do the posedge
and negedge explicitly.  I thought that if I left that out, any state
change for the signal would initiate the block.

	/* cs toggler - cs goes high for one clock cycle every 17 clk_in
cycles */
	always @(posedge clk_in or negedge clk_in) begin
		sck = !sck;
		spi_counter <= spi_counter + 1;
		if (spi_counter == 16)
			cs <= 1;
		if (spi_counter == 17) begin
			cs <= 0;
			spi_counter <= 0;
		end
	end

0
Reply Reza 12/22/2005 9:17:55 AM

johnp wrote:
> Reza -
>
> I suggest you do some studying on your own rather than asking this
> group to design your circuit.
>
> On your tri-state question, try Google "verilog tristate", then do some
> reading.
>
> John Providenza

I have to agree.  No offense, but if you are in an EE graduate level
course, it is shameful that you are asking what a "Digital Design"
course would cover.  And everyone has been more than helpful here.
There are SO many resources available on the Internet with respect to
Verilog and Xilinx CPLD/FPGA's.  I just started working with the group
in our company that does FPGA systems design and there IS a learning
curve.

I have had to do a lot of reading, a lot of RTL coding and simulation,
and a lot of experimentation.  I have asked a couple of questions on
this forum, but have not relied on it for an absolute answer.  Don't
get me wrong.  It is a great resource, but you are doing yourself a
disservice if you won't try to figure this out on your own.  Trust me.
An employer will see this immediately and you won't make it very far.
Just try.

0
Reply mottoblatto 12/22/2005 3:04:17 PM

"If A do a else do b
If !A do b else do a"

In regards to the above.  These statements make "logical" sense.  But
it is BAD design practice when writing RTL code.  It JUST is.  I have
never heard or read any differently.  Put your "reset" condition first,
then follow that with your other conditions.  I don't pretend to be an
expert, so if anyone has a different opinion, please let me know.

I don't know why the synthesizer has a problem with it, but if it not
immediately intuitive at first glance (which it wasn't), then it very
likely will get more difficult to synthesize.  I personally think that
putting the reset condition first like "if (reset condition)..." makes
complete sense.  I don't know.  I guess I have looked at too much RTL
code here, read too many of our format docs, etc to see it any
differntly.  But when you have to write code that will ultimately be
used in an ASIC (not me...others in the company) costing a freaking
ass-ton of money to develop, you tend to keep things consistent.

I would not spend too much time worrying about why your particular
construct wouldn't synthesize.  Instead, focus on the de facto
standards that are used.  Any Verilog book I have seen, and any Verilog
website with examples that I have seen will help.  Writing RTL code is
not a field where you want to be creatively different with regards to
the format.

The best advice I can give is:  Do NOT write ANY code until you know
EXACTLY how the circuit will work.  This includes FF's and the
combinational logic attached to them.  I sometimes draw this out on
paper.  Then you write RTL code using your drawing.  Then it is just
the process of translating that drawing to code, which should be
relatively trivial.

0
Reply mottoblatto 12/22/2005 3:26:35 PM

You've had people recommend that you "think hardware" and I'm of that
camp.  It's one of the reasons for using "templates", each template
corresponds to a specific "piece" of hardware (often called a library
cell in ASIC design, there are similar concepts in FPGA design, but I
don't know if the terminology is changed).  In fact, the original
synthesizers were close to template matchers.  They simply looked at
the code and matched it to a library of templates and if it found a
match, the synthesizer lay down the piece of hardware corresponding to
that template.  

Now synthesizers have grown much smarter, but the basic concept still
holds.  This is why, it is important for you as a designer to follow
the templates carefully.  If you write verilog that matches the
templates, you can predict exactly what kind of hardware the
synthesizer will create.  If your verilog is a little off, the
synthesizer can bend a little to match the templates, but it may do so
by either matching a template that you don't expect or by inserting
extra logic etc.

For example, a "tri-state buffer" in the library I'm failiar with look
like:

        assign out[31:0] = enable ? value[31:0] : 32'bz;

If you put this fragment in your verilog and use the library I
mentioned, you will instantiate 32 parallel 1 bit buffers with a
tri-state enable pin, which copy value to output when the enable is
true and leave the value floating if enable is false.  You can vary
this template to get 32 distinct enable pins--personally, I would
write that as 32 1 bit assignments, but I'm not a chip designer, just
an architect, so there may be a shorter solution.  

However, I would not attempt to put this code into a "clocked always
block".  To me that is tempting the synthesizer to match a different
template than I expected (and tri-state buffers are something I know
have specific semantics that I want followed exactly and not have the
synthesizer "winging it").  That's part of the thinking hardware
aspect.  I have a specific piece of hardware in mind when I write the
verilog code.  I don't mix templates together willy-nilly, as the
synthesizer may figure out what I want and may not.  There are some
places where I allow more latitude, because I know the synthesizer can
generate some circuit that will work and the chip designer can modify
the verilog if the synthesizer doesn't generate a circuit which is
"good enough"--state machines are a good example of where this
latitude is usually ok.

This now bring up the last example, you have given:

>	always @(posedge clk_in or negedge clk_in) begin
....

I don't know what kind of hardware you expect to react exactly to both
rising and falling edges of your clock (and nothing else).  Most
synthesizers don't know of such logic either.  Therefore, this line is
a recipe for disaster.  If you can explain what kind of gates you
expect it to create, there may be another way to write the code.
However, the synthesizers that are complaining that they can't find a
matching template are doing so for good reason.

One final little point on this topic, the code in the templates makes
the verilog behavior match hardware behavior under a set of
assumptions.  These assumptions are normally met under the "clocked
digital design regimen".  That is, if we only look at the values when
things are stable (in between clocks and when things have had enough
time to settle), the behavior the verilog code models and the behavior
the hardware exhibits will match.  However, there are things which
happen in the hardware that don't happen in the verilog model, and
vice versa.  Thus, you can in verilog ask if a signal is floating, but
there probably isn't a piece of hardware that can ask that
question. Designers who forget that the hardware and the verilog
"aren't the same" and only behave the same under controlled
conditions, often write verilog code that corresponds only to
imaginary hardware that can't be built.  Gross violations won't get
through the synthesizer.  More subtle violations will result in pre-
and post- synthesis mismatches or worse a design that simulates but
fails in real hardware under conditions that violate the assumptions
of the simulations.

Hope this helps,
-Chris

*****************************************************************************
Chris Clark                    Internet   :  compres@world.std.com
Compiler Resources, Inc.       Web Site   :  http://world.std.com/~compres  
23 Bailey Rd                   voice      :  (508) 435-5016
Berlin, MA  01503  USA         fax        :  (978) 838-0263  (24 hours)
------------------------------------------------------------------------------

0
Reply Chris 12/22/2005 4:33:08 PM

mottoblatto@yahoo.com wrote:

> The best advice I can give is:  Do NOT write ANY code until you know
> EXACTLY how the circuit will work.  This includes FF's and the
> combinational logic attached to them.  I sometimes draw this out on
> paper.  Then you write RTL code using your drawing.  Then it is just
> the process of translating that drawing to code, which should be
> relatively trivial.

Why not draw the circuit on a computer with a schematic capture
package then? Why the overhead of going through Verilog
and synthesis?

Either that, or your advice is not that good really.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com
0
Reply Jan 12/22/2005 4:35:23 PM

It is good advice if you are just starting out designing using an HDL.
If you don't have a picture of the circuit you are describing, then you
may write crappy code.  I lied.  I do not draw the circuit out.  But I
have in the past when I was first starting with simple logic...like
what the guy is trying to do.  It is SIMPLE.  I can visualize digital
hardware and code from there, but I didn't want to muddy the waters.

Schematic capture would be fine for this example, but defeats the
purpose of trying to learn the HDL.  I'm just trying to give helpful
advice to someone who obviously does not know what is going on.  "What
would a Digital Design class cover?"  Come on.  This guy needs to draw
a circuit!!

I am surprised at your response though.  Being an "electronic design
consultant", I would think that you would agree with what I said.
Maybe it didn't come across well.  I didn't mean "draw your seriously
complex design, and then code it".  Do you write code before you know
what your circuit is going to do, or how it will work?  If so, I
wouldn't use you as a consultant.  Jan.

0
Reply mottoblatto 12/22/2005 4:47:36 PM

Reza Naima wrote:
> Rob,
> 
> I never asked if a microprocessor could read a 'z', I asked if a CPLD
> could determine if an input was floating or not - though I doubt it
> could.  And as I've stated, I'm a graduate student, so I'm obviously
> not working in industry.  I take it you like to skim.
> 
> I found the RTL schematic viewer - though I sitll am not sure what RTL
> stands for.   
> 
> Reza
> 
  RTL = Register Transfer Level.  It means the design is specified in 
the HDL by describing the registers and the logic that goes between it. 
  RTL is generally considered to be device independent, but as giving 
enough detail to make synthesis fairly easy.

Contrast this with a structural description, which is basically a 
netlist containing the FPGA primitives and the wiring connections for 
them.  Structural implementations are device specific, and leave nothing 
for the tools to infer during synthesis; also contrast with  behavioral 
which describes the black box function of the design but not the details 
for the implementation.  Behavioral descriptions are generally not 
synthesizable.
0
Reply Ray 12/22/2005 5:20:11 PM

Reza Naima wrote:
> John,
>
> I'm just trying to use the usenet as a resource to learn.  In reading
> other sources, it seems that I could output a 'z' in order to achieve a
> tri-state -- however, as I've found out, there is a lot of strange
> behaviour in actually going from verilog syntax to application and
> implementation.  I wanted to see if there were any gotcha's in this
> approach.  I also wanted to know if it was possible for a physical
> input to read 'z' if I configure the microcontroller's pin as an input
> (putting it in tri-state), or if I would have to add another pin (say,
> enable_Z) to specify when I want the output to be equal to 'z'.  I'm
> also not sure about the implementation differences - say, between
> xilinx and altera, and if one supports a certain mode of opperation
> that the other does not.

Turns out that both Altera's and Xilinx' proprietary synthesis tools,
as well as Synplify and Mentor Precision, use the same constructs to
infer tristate buffers.

And it turns out that all four tools have documentation that clearly
explains how to infer a tristate!

R T F M.  Really.

> Another aspect of my questions is trying to understand the strange
> behaviour.  I still don't see why the synthesizer has a problem
> equating these two constructs :
>
> If A do a else do b
> If !A do b else do a
>
> they seem identical to me, and I'll have to do some more research and
> re-read some of the replies to this thread to try to figure it out.

In the specific case of the reset circuit, you have to realize
something.   Perhaps the circuit has an active low reset.  In that
case, the condition

    if (reset_n)
        q <= q + 1;
    else
        q <= 0;

has a different meaning than

    if (~reset_n)
        q <= 0;
    else
        q <= q + 1;

Even though at first glance they appear identical.

You must realize that the async reset _has priority_ over the rest of
the logic, so you must write your code to reflect that.  The synthesis
tool helpfully complains if you do it wrong.

-a

0
Reply Andy 12/22/2005 9:56:29 PM

mottoblatto@yahoo.com wrote:
> "If A do a else do b
> If !A do b else do a"
>
> In regards to the above.  These statements make "logical" sense.  But
> it is BAD design practice when writing RTL code.  It JUST is.  I have
> never heard or read any differently.  Put your "reset" condition first,
> then follow that with your other conditions.  I don't pretend to be an
> expert, so if anyone has a different opinion, please let me know.
>
> I don't know why the synthesizer has a problem with it,

PRIORITY!!!!

The async reset has priority over the synchronous (clocked) logic.
That's why its condition is handled FIRST.

-a

0
Reply Andy 12/22/2005 9:58:53 PM

Reza Naima wrote:

> - The async verilog code will only be run once every few days, and will
> be controlled from a microcontroller that I can tweak to guarantee
> sufficient time between each state change.  I do have a clock available
> that I could feed into it to make it a synchronous design - but I'll go
> for the async first to see if I can get it to work.

How often the code runs is irrelevant.  The question is how long
between changes must you wait for all affected logic to settle.

> p.s. I've added some extra code (see below) that is synthesized just
> fine on one of the xilinx CPLDs, but gives errors if I configure it for
> another CPLD types.

If you're referring to the code below, I say: Impossible.

> It says it can't find a matching template for the
> other cpld architectures.   I also found that I had to do the posedge
> and negedge explicitly.

It's perfectly legal to use both sides of the clock for different
flip-flops.  However, there's no CPLD/FPGA flip-flop that is sensitive
to both edges of the clock.

> I thought that if I left that out, any state
> change for the signal would initiate the block.

No -- the only things that "initiate" the block are the signals on the
sensitivity list.  Which is why a sensitivity list exists.

> 	/* cs toggler - cs goes high for one clock cycle every 17 clk_in
> cycles */
> 	always @(posedge clk_in or negedge clk_in) begin
> 		sck = !sck;
> 		spi_counter <= spi_counter + 1;
> 		if (spi_counter == 16)
> 			cs <= 1;
> 		if (spi_counter == 17) begin
> 			cs <= 0;
> 			spi_counter <= 0;
> 		end
> 	end

-a

0
Reply Andy 12/22/2005 10:06:01 PM

>I found the RTL schematic viewer - though I sitll am not sure what RTL
>stands for.   

google works pretty well for that sort of problem.  If you can't find
something interesting right away, add acronym to the search list.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.

0
Reply hmurray 12/23/2005 6:01:45 PM

Wow, this thread had hit the 40 post mark already.  First off, I want
to thank all the people that have given me a great deal of help and
insight in understanding verilog/synthesizers.  It seems my biggest
problem was that I though that HDL would give me the ability to write
behavioral code and the software would be able to make it work - i.e.
if I add a delay, it generates all the required counters/etc to
implment the delay.  But it seems to be a lot more primative than I had
expected.

However, I am a bit irked at the continued comments about this "digital
design" class.  I have no problems taking a course that's recommended,
but when I try to map "digital design" to a real course and ask for
help doing so, I get nothing but degrading comments.  So, I will ask
one last time in a more direct fasion: Rather than degrading my
abilities, please find a "digital design" class from the Berkely course
schedule.  http://schedule.berkeley.edu .  I also want to follow by
saying that I am not an EE major nor have I taken any EE classes in my
life.  I'm a bioengineering major and the bulk of my courses have been
dealt with mechanics, chemistry, physics, biology, etc.  With that
said, I have done a lot of electronics work - mostly with
microcontrollers, and the work I've done has been well liked by the
people I have worked for.

I think of verilog/HDL as a tool to use, not a career destination.
All I want is a rudementary understanding of it so I can later make
informed decisions about what the right tool to use for a task is.

And getting back to the notion of asking questions vs. doing my own
"studying" -- I've learned more in the past 40 posts about
verilog/synthesizers than I have in the dozens of hours I've spent
reading books and web pages on the material.  And in response to the
RTFM, I actually followed someone else's suggestion of googling for
"tristate verilog".  I found some docs for altera, whch didn't seem to
work for xilinx.  After  bit of playing, I figured it out.  I
appreciate that you answered my question, twice, but there was no need
to be insultive about it.  I really didn't know where to look about the
tristate thing - you could have said "look in the xxxxx docs" or given
me the answer and had that been the end of it.

One other comment before I ask some real questions.  I really want to
thank the people that have posted brief and accurate answers to my
questions as well as those that have provided me with pointers.

Ok, Real questions in response :

- Are there a standard set of templates that all synthesizers use?  The
problem was that the same synthesizer said it couldnt find a template
for one target CPLD, but it found it for another.  Why would this be?
Does anyone know of a respository for standard templates?
-  There have been several replies indicating that the order of the
statment has to do with priorities, and an async reset has a higher
priority.  Why is this?  Is this just how flipflops are physically
built?  Andy gave an example about a high vs. low reset.   Was the
second example invalid?   My code "if (!reset)..." failed, but what if
it was an active low reset.  Then shouldn't it have worked?  Or was the
reset implied in the <= 0, in which case the problem was not the
(!reset), but rather the location of <=0?  What exactly defines a
reset?
- about the rising & falling edge of a signal triggering a block - if
two flipflops are required, so be it.  is it bad form?  Shouldn't the
synthesizer be able to deal with it?

thnx,
reza

p.s. people keep saying there are great resources on the net, but i'm
having problems finding good information.  If anyone knows of some good
sites, I would love to know.  google is not a valid answer to this
question, but google search terms are if you've found good info using
the phrase.

0
Reply Reza 12/25/2005 10:03:40 AM

Hi Reza!


I will recommend two readings that will save you a lot of headache:

The first one is an expensive, but invaluable book (sorry, don't know
if it exists in a Verilog version): "VHDL for Logic Synthesis"


And the second one is a free PDF downloadable from Actel homepage:
"Actel HDL Coding"

(I am sure the other players have their own HDL coding style guides
too, but this one looks the best).

They will show you how synthesizers work internally.

good luck!
(and happy new year)



PS. for some reason some people one the newsgroups waste a lot of their
own time and our time by giving non-answers. If you dont have an
answer, dont post!!

0
Reply burn 12/25/2005 1:10:10 PM

Reza Naima wrote:
> Wow, this thread had hit the 40 post mark already.  First off, I want
> to thank all the people that have given me a great deal of help and
> insight in understanding verilog/synthesizers.  It seems my biggest
> problem was that I though that HDL would give me the ability to write
> behavioral code and the software would be able to make it work - i.e.
> if I add a delay, it generates all the required counters/etc to
> implment the delay.  But it seems to be a lot more primative than I had
> expected.

Yes. You'll have to scale down such expectations about synthesis
drastically.

> I think of verilog/HDL as a tool to use, not a career destination.

That may explain your communication problems with many of the people
here.

On a personal note, the meta-goal of my current work is to show that
your approach is meaningful and productive. You may want to
explore the link in the signature section.

> - Are there a standard set of templates that all synthesizers use?

There is an IEEE synthesis standard that all reasonable synthesis tools
will adhere to - but I agree that it doesn't seem that easy to get that
info for free.

My advice: for implementation-oriented modeling, you only need 2
templates: the synchronous always block (sensitive to a clock
edge and possibly a reset edge), and the combinatorial always
block (sensitive to the input signal levels).

Out of these, use the synchronous template for the bulk of your
work. The big advantage is that you can then raise your expectations
again. To a large extent, you can concentrate on getting the behavior
right (hard enough), and rely on the synthesis tool to give you a good
implementation. In contrast to what many people will tell you (and
sometimes shout at you), there's no need to try to visualize the exact
hardware that will come out. Believe me, they can't either.

I'll go further. Once you follow the advice above, relying on
"hardware thinking" too much will hamper productivity. Die-hard
hardware thinkers may miss the opportunity to find an elegant coding
solution without giving up efficiency in the synthesized result. So
here's a chance to do better than the experts.

> -  There have been several replies indicating that the order of the
> statment has to do with priorities, and an async reset has a higher
> priority.  Why is this?  Is this just how flipflops are physically
> built?

I think they just implement what "asynchronous" means. Priority
seems an inherent property.

> - about the rising & falling edge of a signal triggering a block - if
> two flipflops are required, so be it.  is it bad form?  Shouldn't the
> synthesizer be able to deal with it?

To me, it's not obvious they should. A particular case is not
a general solution yet.

For now, just code the behavior you want using two
synchronous blocks, sensitive to different edges.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com
0
Reply Jan 12/25/2005 10:39:25 PM

I seem to have missed some articles in this thread, as there are some
things being reference that I can't having seen.  However, I would
like to respond to some of the last comments I've seen.

Reza Naima wrote:
> It seems my biggest problem was that I though that HDL would give me
> the ability to write behavioral code and the software would be able
> to make it work...

Yes, that is always the hitch--in every area where we have automated
tools: synthesizers, parser generators (my area of expertise), 4GL
lanugages, natural language translators, et al.  There is some level
of behavioral code that tools will be able translate.  However, they
will never reach the "holy grail".  This is no "dwim" (do what I mean)
instruction and cannot be.  What we have are idioms that tools can
understand and paraphrase.  If you learn the idioms (dialect) the tool
can speak, you can make it do quite a bit.  

Here is some very specific advice about what idioms that synthesizers
understand.

Jan Decaluwe wrote:
> My advice: for implementation-oriented modeling, you only need 2
> templates: the synchronous always block (sensitive to a clock
> edge and possibly a reset edge), and the combinatorial always
> block (sensitive to the input signal levels).

This is the essence of a digital design course.  Laying down
combinatorial logic that is fed into (or driven by) a set of
flip-flops that are clocked at an appropriate time.  At some very deep
level all synchronous digital design is about designing an FSM (finite
state machine) which is merely a collection of gates around
flip-flops.

J> To a large extent, you can concentrate on getting the behavior
> right (hard enough), and rely on the synthesis tool to give you a good
> implementation.

This is true.  If you build everything, out of the two blocks
described, you will have designed a circuit that a synthesizer can
build.  There are still timing issues and other things to worry about.
However, the synthesizer will be able to lay down a set of gates that
does what your model does.  This is the technology that the
syntehsizer writers' have, a way of translating those two idioms into
circuitry.  Those are probably about the only two universal idioms,
because they represent things that are present in all forms
(implementations) of Boolean logic.

Things like tri-state drivers are not universal, because they are not
purely parts of Boolean logic and some implementations will have them
and others may not.  Moreover, they may work "differently" in varying
implementations, because the underlying mechanism may work
"differently", and that may require specifying them differently at the
source level, to give a better interpretation of the semantics of the
implementation.

J> In contrast to what many people will tell you (and sometimes shout
> at you), there's no need to try to visualize the exact hardware that
> will come out. Believe me, they can't either.

Here I will disagree to some extent.  Jan is correct in that I can't
predict exactly what gates will be infered by a synchronous always
block I write.  However, I do have a reasonable expectation, that it
will be some combinatorial logic feeding some flip-flops and some
combinatorial logic leading away from the flip-flops.  Moreover, when
I've written a synchronous always block, I have a pretty code idea
what signal is going to be driving the clock pins of the flip-flops in
that block.  Now, if I want something different, say a tri-state bus
with some keeper that has a specific decay on it, I will write
different Verilog code.  I will be really surprised if a synthesizer
writes out a tri-state bus when I've written a synchronous always
block--the synchronous always block is not the idiom used to create a
tri-state bus.

This is what I mean, by think hardware.  Learn the idioms and what
they translate to.  There aren't many of them.  I think I know about
5: combinatorial code, synchronous (clocked) always block, tri-state
driver, priority encoder, and mux.  Once you've learned the idioms,
then you know when you want something that works like x, you pick the
idiom that generates an x.  Now, you may not know all the hardware the
synthesizer will generate to lay down an x (and the synthesizer may
even be more clever than you are and know that a y will work in the
given context and substitute a y), but you'll have basic concepts of
what the synthesizer can do for you and you will design circuits which
the synthesizer can lay down.  When I want to design something, I
think how I can build it using those basic concepts, and once I know
that I can build it out of those things, then I have a rough design.
If I want something that I can't map to those concepts, then I don't
know how to build it (and I don't know what to tell the synthesizer
either).

Not to beat a dead horse, but I have one final comment on the topic
of "thinking in hardware".  It has to do with for-loops.  There are
some for loops that can be synthesized, but many (most) cannot.  In
general for-loops that search cannot by synthesized.  Nor can ones
that do sorting.  For-loops that simply iterate over each bit of a
resigter can.  If one lays down an unsynthesizable for-loop in an
otherwise synthesizable always block, the result is unsynthesizable.
The whole point of "thinking in terms of hardware" is avoiding writing
that kind of code.

Finally, I don't have a good answer to:

R> -  There have been several replies indicating that the order of the
> statment has to do with priorities, and an async reset has a higher
> priority.  Why is this?  Is this just how flipflops are physically
> built?

It's probably more likely an artifact of the synthesizer.  As I said
previoiusly, the synthesizer works by matching your code to its
templates.  Those templates have some assumptions built into them.
Now, there are some variations in the templates the synthesizer can
handle (and better synthesizers generally can handle more variation).
However, at some level, when you've strayed too far from the
templates, the synthesizer writer cannot legitimately infer what you
"meant" and the writer chooses instead to give you an error telling
you to change your code into something that better matches the
templates (rather than instantiating something that is wrong).

Hope this helps,
-Chris

*****************************************************************************
Chris Clark                    Internet   :  compres@world.std.com
Compiler Resources, Inc.       Web Site   :  http://world.std.com/~compres  
23 Bailey Rd                   voice      :  (508) 435-5016
Berlin, MA  01503  USA         fax        :  (978) 838-0263  (24 hours)
------------------------------------------------------------------------------
0
Reply Chris 12/27/2005 9:39:01 PM
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Hello, I am new to the java envoierment. I have several questions regardingthis language:1. How about using class initializer ? When it is run ? If i include a classfrom package, will it be also an initializer run for every class in thatpackage ?2. I have problem with this code :// FILE primer.javaimport static narzedzia.LiczbyPierwsze ;public class primer { public static void main(String[] args) { LiczbyPierwsze.main(); // TODO, add your application code System.out.println("Hello World!"); }}// FILE LiczbyPierwszepackage narzedzia;public class LiczbyPierwsze {p...