I am designing usin an xc9500 Xilinx PLD and i observed some strange
behavior, wondering if anyone can confirm or deny.

It appears that a macrocell is used for each output pin (or
bidirectional).   I get a summery like this:

Total Macrocells Available  216
 Registered Macrocells  124
 Non-registered Macrocells driving I/O  48


My design has about 120 macrocells, and these 48 dirving are bothering
me.  Why does it need a macrocell for the I/O.  I put the chip in low
power output mode, hoping that would free them up, but no luck.


Mike D

MikeD wrote:

> I am designing usin an xc9500 Xilinx PLD and i observed some strange
> behavior, wondering if anyone can confirm or deny.
> 
> It appears that a macrocell is used for each output pin (or
> bidirectional).   I get a summery like this:
> 
> Total Macrocells Available  216
>  Registered Macrocells  124
>  Non-registered Macrocells driving I/O  48

I think beyond this 48 pins you have other pins that are driven by registed
macrocells too.

> 
> 
> My design has about 120 macrocells, and these 48 dirving are bothering
> me.  Why does it need a macrocell for the I/O.  I put the chip in low
> power output mode, hoping that would free them up, but no luck.

I read the XC9500 user manual and I think it is designed so that you need
one macrocell for each output pin.

vax, 9000

> 
> 
> Mike D

"vax, 9000" <vax9000@gmail.com> schrieb im Newsbeitrag
news:cvlkvg$64i$1@charm.magnus.acs.ohio-state.edu...

> > me.  Why does it need a macrocell for the I/O.  I put the chip in low

> I read the XC9500 user manual and I think it is designed so that you need
> one macrocell for each output pin.

Exactly. With the coolrunners, there is an option to use IO and macrocell
independend, but I wouldnt base my design too much on it. Use a bigger CPLD
or FPGA.

Regards
Falk