Hi,
I'm debugging the old design which now has been complemented with the 
MIG core accessing the DDR2 memory (platform: SP601, coded in VHDL).
To analyze problems with not working MIG core, I have switched the 
debugging on, and added the chipscope definition (.cdc) file.
However now, when I try to compile the design, I get errors like this:

Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'memctl_1/gen_dbg_enable.my_vio_c3' with type
   'vio' could not be resolved. A pin name misspelling can cause this, a missing
   edif or ngc file, case mismatch between the block name and the edif or ngc
   file name, or the misspelling of a type name. Symbol 'vio' is not supported
   in target 'spartan6'.
ERROR:NgdBuild:604 - logical block 'memctl_1/gen_dbg_enable.my_icon_c3' with
   type 'icon' could not be resolved. A pin name misspelling can cause this, a
   missing edif or ngc file, case mismatch between the block name and the edif
   or ngc file name, or the misspelling of a type name. Symbol 'icon' is not
   supported in target 'spartan6'.
ERROR:NgdBuild:604 - logical block 'memctl_1/gen_dbg_enable.my_ila_c3' with type
   'ila' could not be resolved. A pin name misspelling can cause this, a missing
   edif or ngc file, case mismatch between the block name and the edif or ngc
   file name, or the misspelling of a type name. Symbol 'ila' is not supported
   in target 'spartan6'.

Should I add a library to my top-level entity to clear this problem?
Or should I add some additional sources?
-- 
TIA & regards,
WZab

If you have generated the chipscope cores using coregen then the path to
the edif files needs to be added to your ISE project. Otherwise if you have
created a chipscope project in ISE then the edif files will be created
before the design is synthesised and p&r.

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Dnia 17.10.2010 maxascent <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
> If you have generated the chipscope cores using coregen then the path to
> the edif files needs to be added to your ISE project. Otherwise if you have
> created a chipscope project in ISE then the edif files will be created
> before the design is synthesised and p&r.

Thanks,

I've just stated, that I have to add the xco files generated by MIG:
user_design/par/icon_coregen.xco
user_design/par/via_coregen.xco
user_design/par/ila_coregen.xco

This process builds the icon.ngc, via.ngc and ila.ngc
files, which I can add to my design to compile it successfully.
-- 
Thanks, WZab