Hi all,

I am sorry if this problem has been answered but I cannot find much help 
from the archive.

I am trying to test the SRAM on the S3 starter kit board with the 
following code:

if ToWrite then
	data_buffer <= "00000000000000001111"; --A
	sram_io <= data_buffer;
	data_buffer <= "00000000000000000101"; --B
else
	sram_io <= (others=>'Z');
	led_out(0) <= sram_io(0);
	led_out(1) <= sram_io(1);
	led_out(2) <= sram_io(2);
	led_out(3) <= sram_io(3);
end if;


The output on the leds keep showing the result B (ie "0101") instead of 
"1111".

Please help!~

On 2008-01-14, Nick <tklau@cuhk.edu.hk> wrote:
> 	data_buffer <= "00000000000000001111"; --A
> 	sram_io <= data_buffer;
> 	data_buffer <= "00000000000000000101"; --B

I don't speak VHDL, but in Verilog if you wrote something like that
in a process that happened on every clock, the first assignment of
data_buffer would be overridden by the second.  If you want a series
of steps (outside of simulation) you're going to have to do it with
some kind of counter or state machine.

Eg:

	data_buffer <= phase_a ? 20'b1111 : 20'b0101;

(in Verilog, but you get the idea)

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

In this case the VHDL is working the same way a piece of Verilog code would. 
The signal does change just as it would in verilog but the value change 
occurs in 0 time.   You are quite right that the previous code needs a state 
machine controling it inoder to have data_buffer<="0000_0000_0000_0000_1111" 
written.
"Ben Jackson" <ben@ben.com> wrote in message 
news:slrnfom4gj.25b0.ben@saturn.home.ben.com...
> On 2008-01-14, Nick <tklau@cuhk.edu.hk> wrote:
>> data_buffer <= "00000000000001111"; --A
>> sram_io <= data_buffer;
>> data_buffer <= "00000000000000000101"; --B
>
> I don't speak VHDL, but in Verilog if you wrote something like that
> in a process that happened on every clock, the first assignment of
> data_buffer would be overridden by the second.  If you want a series
> of steps (outside of simulation) you're going to have to do it with
> some kind of counter or state machine.
>
> Eg:
>
> data_buffer <= phase_a ? 20'b1111 : 20'b0101;
>
> (in Verilog, but you get the idea)
>
> -- 
> Ben Jackson AD7GD
> <ben@ben.com>
> http://www.ben.com/ 

Thank you! You're right! The 2nd assignment overrode the 1st one.


Dwayne Dilbeck wrote:
> In this case the VHDL is working the same way a piece of Verilog code would. 
> The signal does change just as it would in verilog but the value change 
> occurs in 0 time.   You are quite right that the previous code needs a state 
> machine controling it inoder to have data_buffer<="0000_0000_0000_0000_1111" 
> written.
> "Ben Jackson" <ben@ben.com> wrote in message 
> news:slrnfom4gj.25b0.ben@saturn.home.ben.com...
>> On 2008-01-14, Nick <tklau@cuhk.edu.hk> wrote:
>>> data_buffer <= "00000000000001111"; --A
>>> sram_io <= data_buffer;
>>> data_buffer <= "00000000000000000101"; --B
>> I don't speak VHDL, but in Verilog if you wrote something like that
>> in a process that happened on every clock, the first assignment of
>> data_buffer would be overridden by the second.  If you want a series
>> of steps (outside of simulation) you're going to have to do it with
>> some kind of counter or state machine.
>>
>> Eg:
>>
>> data_buffer <= phase_a ? 20'b1111 : 20'b0101;
>>
>> (in Verilog, but you get the idea)
>>
>> -- 
>> Ben Jackson AD7GD
>> <ben@ben.com>
>> http://www.ben.com/ 
> 
>