I am implementing a design using Virtex-6 Device:XC6VLX550T Package:FF1759 =
and Speed:-2.

My top module instantiates 16 units, where each unit instantiates 18x8 mult=
iplier 49 times. This means that my design is using 784 multipliers. The nu=
mber of DSP48 modules available on the Virtex-6 device is 864 which means t=
hat less than 100% of resources are used.=20

However, when I synthesize my design, I see this information:=20
Primitive and Black Box Usage:
------------------------------
# IO Buffers                       : 26946
#      IBUF                        : 6562
#      OBUF                        : 20384
# Others                           : 784
#      xcorr_mult_18x8             : 784

Device utilization summary:
---------------------------

Selected Device : 6vlx550tff1759-2=20


Slice Logic Utilization:=20

Slice Logic Distribution:=20
 Number of LUT Flip Flop pairs used:      0
   Number with an unused Flip Flop:       0  out of      0        =20
   Number with an unused LUT:             0  out of      0        =20
   Number of fully used LUT-FF pairs:     0  out of      0        =20
   Number of unique control sets:         0

IO Utilization:=20
 Number of IOs:                       26946
 Number of bonded IOBs:               26946  out of    840   3207% (*)=20


The Mapping report shows:
Interim Summary
---------------
Slice Logic Utilization:
  Number of Slice Registers:                     0 out of 687,360    0%
  Number of Slice LUTs:                          0 out of 343,680    0%

Slice Logic Distribution:
  Number of LUT Flip Flop pairs used:            0

IO Utilization:
  Number of bonded IOBs:                    26,946 out of     840 3207% (OV=
ERMAPPED)

Specific Feature Utilization:
  Number of RAMB36E1/FIFO36E1s:                  0 out of     632    0%
  Number of RAMB18E1/FIFO18E1s:                  0 out of   1,264    0%
  Number of BUFG/BUFGCTRLs:                      0 out of      32    0%
  Number of ILOGICE1/ISERDESE1s:                 0 out of   1,440    0%
  Number of OLOGICE1/OSERDESE1s:                 0 out of   1,440    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHCEs:                             0 out of     216    0%
  Number of BUFOs:                               0 out of      72    0%
  Number of BUFIODQSs:                           0 out of     144    0%
  Number of BUFRs:                               0 out of      72    0%
  Number of CAPTUREs:                            0 out of       1    0%
  Number of DSP48E1s:                          784 out of     864   90%
  Number of EFUSE_USRs:                          0 out of       1    0%
  Number of FRAME_ECCs:                          0 out of       1    0%
  Number of GTXE1s:                              0 out of      36    0%
  Number of IBUFDS_GTXE1s:                       0 out of      18    0%
  Number of ICAPs:                               0 out of       2    0%
  Number of IDELAYCTRLs:                         0 out of      36    0%
  Number of IODELAYE1s:                          0 out of   1,440    0%
  Number of MMCM_ADVs:                           0 out of      18    0%
  Number of PCIE_2_0s:                           0 out of       2    0%
  Number of STARTUPs:                            1 out of       1  100%
  Number of SYSMONs:                             0 out of       1    0%
  Number of TEMAC_SINGLEs:                       0 out of       4    0%


Mapping completed.
See MAP report file "xcorr_pixel_channel_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   2
Number of warnings :   0

Section 1 - Errors
------------------
ERROR:Pack:2309 - Too many bonded comps of type "IOB" found to fit this dev=
ice.
ERROR:Map:237 - The design is too large to fit the device. Please check the=
 Design Summary section to see which resource requirement for your design e=
xceeds the resources available in the device. Note that the number of slice=
s reported may not be reflected accurately as their packing might not have =
been completed.

NOTE: An NCD file will still be generated to allow you to examine the mappe=
d design. This file is intended for evaluation use only, and will not proce=
ss successfully through PAR.
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

How can I reduce the number of Bonded IOBs?

Note: I have not specified an User Constraint File (.ucf) yet, as I am dete=
rmining whether the design will fit or not on the selected FPGA.

Thanks in advance.

In article <c7672a44-b425-4842-81cb-808300f85b7b@glegroupsg2000goo.googlegroups.com>,
Vivek Menon  <comp.arch.fpga@googlegroups.com> wrote:
>I am implementing a design using Virtex-6 Device:XC6VLX550T Package:FF1759 =
>and Speed:-2.
>
>My top module instantiates 16 units, where each unit instantiates 18x8 mult=
>iplier 49 times. This means that my design is using 784 multipliers. The nu=
>mber of DSP48 modules available on the Virtex-6 device is 864 which means t=
>hat less than 100% of resources are used.=20

I suspect you're instantiating a unit whose multipliers have the
output and one input marked as connected to the outside world; you
seem to have about eight inputs and 18+8 outputs per multiplier.

Obviously the FPGA doesn't have the thirty thousand pins that would imply!

Tom