Safe State Machine Design in AHDL
Hello, I was curious if anyone can comment on writing safe state
machines in AHDL. I often use One-hot encoding in my state machines and
am curious how safe it is. I set the State Machine setting in Quartus
for One-hot Encoding, does this force all my state machines to be safe.
If I just add the line to my state machine:
When Others => StateMachine = StateA; -- go back to start
will the state machine be considered safe?
Yes and no.
The real questions is: "safe from what?". State machines just don't go wild
out of blue.
In fact, this question is very hard to a...Safe finite state machine design
I am programming a Xilinx FPGA using Xilinx Project Navigator tool and
FPGA Express for synthesis.
I want to design a "safe" FSM, where the machine would fall back to
reset state when it goes in an illegal state (I am using one-hot
At the end of the case statement listing all states, I included a
"when others" clause that should make the machine go back to reset
state if it is stuck in a state that is not listed (an illegal state).
In FPGA Express, I selected the option "FSM Synthesis: Interpretation
of VHDL 'when others': safest (all possibl...problem with a state machine
I've got a problem with a state machine that i'm modeling for the
communication with the PDIUSB12-chip for USB communication:
(By the way - do you know if there is already an existing vhdl-code for this
task to download somewhere?)
I did a state machine for writing with 5 states, and in the state
"WRITE_INIT" i need to do a write of 3 bytes (one every clock cycle). But as
I simulate my code with modelsim, it never gets to the 2nd byte, it just
stops. I cannot understand it!
THANK YOU! :-)
Here is the part of my code:
PROCESS (reset,CLK, next_sreg)
...State machine problem
Hi,This is my first attempt to use state machine in my project. I adopted the standart machine from LV. I tried to add a new frame "Hardware Init" and LV started to give me an error which has to do with the ENUM value. Could someone explain how to properly add states to my state machine? Also I would like to know how to make sure that all inputs will be on the left and all outputs will be on the right, so that my wires will stay neat and program will be easy to read. Thanks.Message Edited by RSibagatullin on 06-25-2008 02:20 PM
http://forums.ni...State Machine with a for loop problem...
I'm working on a state machine where I need to implement basically a
for-loop with in a state machine and have run into a problem.
I'm using Xilinx Foundation 7.1SP4, working in VHDL, targeting a
Virtex-II. I have it setup where I can ouput signals to a logic
analyzer to see what's going on.
Here's how I define my states:
type MAIN_STATE_TYPE is (M0, M1, M2, M3, M4, M4A, M4B, M5, M5A, M6, M7,
M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20);
signal MCS, MNS: MAIN_STATE_TYPE;
Here's my process to go from one state to the next:
b...state machine dead problem
I am having a very stange problem with my state machine. The state
machine turns dead after some uncertain time(20min ~ 2 days) and all
outputs of the statemachine are 0. All other logics in the chips work
properly at the same time. The state machine is very simple, only with
8 states. I tried with StateCAD and programming manually with VHDL and
they behave the same. Anybody know what's possibly the problem? I have
been working on this for a week and really cannot find a way out.
> I am having a very stange problem with my state machine. The state
&...problem with synthesis of a state machine
The following code runs well in simulation mode but synthesis fails.
Please let me know how I can get this synthesized, thanks!
`timescale 1ns / 1ps
module blink_led(clk, d, led);
output wire led;
parameter blink_freq = 2;
reg [blink_freq:0] count = 0;
reg [1:0] state = 0;
reg [1:0] next_state = 0;
assign led = !count[blink_freq];
always @(posedge clk)
state <= next_state;
if(state == 2'b01)
count <= count + 1;
next_state <= 2'b10;
next_state <= 2'b01;
always @(state o...State machine design question
I am designing a a/v capture application. The user can monitor a
live scene and at any time start capturing to file. While capturing
to file he can mark the start and end times of interesting regions so
that a playback application later can just playback the clips of
I thought this might be represented well with a state machine. There
seem to be several overlapping states.
- Streaming & Capturing
- Streaming & Capturing & Marking
In order to switch between streaming and Streaming & Capturing, the
system needs to be stopped ...state machine problem in vhdl
I am facing problem with the following process.
state machine from state "0001" goes to state "0011" instead of "0010"
when the wr signal is low.
Can u suggest something ?
PROCESS (rst, extclk) --PROCESS no 01
IF rst = '0' THEN
temp_w <= "0000";
wrpointer_tx <= (OTHERS => (OTHERS => '0'));
wren_txram <= '0';
wraddress_txram <= (OTHERS => '0');
ELSIF rising_edge(extclk) THEN