On Sep 23, 7:56=A0pm, rickman <gnu...@gmail.com> wrote: > I was looking up the shift operator in VHDL since I seldom use it and > saw that there is both a shift left logical and a shift left > arithmetic. =A0The logic shift left shifts in zeros and the arithmetic > shift left shifts in the value of the lsb. > > I remember from school how a shift right can be logical or arithmetic > in order to implement signed and unsigned arithmetic. =A0But when > shifting left, I have always used a single shift operator, the logical > shift. > > If an arithmetic left shift is used, it gives a valid result for some > values, assuming that the "valid" result is the same as multiplying by > 2**n. =A0But the arithmetic left shift does not fit that model for other > values. =A0On the other hand, the logical left shift *always* returns a > value that is the 2**n multiple of the input value, assuming there are > no range issues such as overflowing into the sign bit. > > So I don't understand the utility of the arithmetic left shift > operator and I especially don't see the reason for calling it > "arithmetic". =A0Can anyone shed some light on this? > > Rick how is this related to FPGA? try vhdl newsgroup? Antti

0 |

9/23/2009 4:59:57 PM

On Wed, 23 Sep 2009 09:59:57 -0700 (PDT), Antti wrote: >how is this related to FPGA? >try vhdl newsgroup? Well... it is somewhat relevant. And comp.lang.vhdl is being spammed mercilessly right now by some bozo trying to sell fake sneakers. And Rick well knows that many of the usual comp.lang.vhdl suspects also hang out here. So it's not so crazy. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

0 |

9/23/2009 5:51:11 PM

On Sep 23, 8:51=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Wed, 23 Sep 2009 09:59:57 -0700 (PDT), Antti wrote: > >how is this related to FPGA? > >try vhdl newsgroup? > > Well... it is somewhat relevant. > And comp.lang.vhdl is being spammed > mercilessly right now by some bozo trying > to sell fake sneakers. =A0And Rick well knows > that many of the usual comp.lang.vhdl suspects > also hang out here. =A0So it's not so crazy. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. ic comp . arch . embedded is also sneaker victim im not monitoring vhdl so wasnt aware its sneaker infection ok, that valid excuse ;) Antti

0 |

9/23/2009 6:21:38 PM

Antti.Lukats@googlemail.com <antti.lukats@googlemail.com> wrote: < On Sep 23, 7:56?pm, rickman <gnu...@gmail.com> wrote: <> I was looking up the shift operator in VHDL since I seldom use it and <> saw that there is both a shift left logical and a shift left <> arithmetic. ?The logic shift left shifts in zeros and the arithmetic <> shift left shifts in the value of the lsb. <> I remember from school how a shift right can be logical or arithmetic <> in order to implement signed and unsigned arithmetic. ?But when <> shifting left, I have always used a single shift operator, the logical <> shift. (snip) <> So I don't understand the utility of the arithmetic left shift <> operator and I especially don't see the reason for calling it <> "arithmetic". ?Can anyone shed some light on this? In software (languages such as C and Fortran) the difference is in the possible consequence of overflow. Computing hardware does support arithmetic left shift: http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/BOOKS/dz9zr003/7.5.116 such that the sign bit does not participate in the shift. < how is this related to FPGA? try vhdl newsgroup? For questions related to synthesis, it doesn't seem so far off to post here. For questions only related to simulation, or language syntax questions, it does seem a little off topic. In this case, I suppose it could be used in synthesis, but it isn't so obvious. -- glen

0 |

9/23/2009 7:08:45 PM

On Sep 23, 3:08=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Antti.Luk...@googlemail.com <antti.luk...@googlemail.com> wrote: > > < On Sep 23, 7:56?pm, rickman <gnu...@gmail.com> wrote: > <> I was looking up the shift operator in VHDL since I seldom use it and > <> saw that there is both a shift left logical and a shift left > <> arithmetic. ?The logic shift left shifts in zeros and the arithmetic > <> shift left shifts in the value of the lsb. > > <> I remember from school how a shift right can be logical or arithmetic > <> in order to implement signed and unsigned arithmetic. ?But when > <> shifting left, I have always used a single shift operator, the logical > <> shift. > (snip) > > <> So I don't understand the utility of the arithmetic left shift > <> operator and I especially don't see the reason for calling it > <> "arithmetic". ?Can anyone shed some light on this? > > In software (languages such as C and Fortran) the difference is > in the possible consequence of overflow. =A0 > > Computing hardware does support arithmetic left shift: > > http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/BOOKS/dz9zr003/7.5.116 > > such that the sign bit does not participate in the shift. =A0 Yes, but this is not an arithmetic left shift as defined by my original post. "For SLA or SLAG, zeros are supplied to the vacated bit positions on the right" That is what I was taught was the way to perform an arithmetic left shift, to fill the right positions with zero. But this is also the logical left shift operation. I don't understand why a left shift which fills the right most positions with the former lsb would be of value. I suppose it could just exist to fill the space in a chart, but calling it an arithmetic left shift is a misnomer as arithmetic would use the same shift as the logical left shift. To make Antti happy, ignore the use of the abbreviation VHDL in my original post. This is about an arithmetic algorithm as used in an FPGA I am designing. Rick

0 |

9/23/2009 8:19:05 PM

rickman wrote: > That is what I was taught was the way to perform an arithmetic left > shift, to fill the right positions with zero. But this is also the > logical left shift operation. I don't understand why a left shift > which fills the right most positions with the former lsb would be of > value. I suppose it could just exist to fill the space in a chart, > but calling it an arithmetic left shift is a misnomer as arithmetic > would use the same shift as the logical left shift. But only because you suppose that the MSB is on the left side and the LSB on the right side.

0 |

9/23/2009 9:47:48 PM

> On Sep 23, 7:56 pm, rickman <gnu...@gmail.com> wrote: >> I was looking up the shift operator in VHDL since I seldom use it and >> saw that there is both a shift left logical and a shift left >> arithmetic. The logic shift left shifts in zeros and the arithmetic >> shift left shifts in the value of the lsb. sla shifts left and copies the right bit. Use of sla and sll on std_logic_vector is depreciated since numeric_standard.shift_left automatically does the "right thing" with the edge bits for signed or unsigned types. Antti.Lukats@googlemail.com wrote: > how is this related to FPGA? VHDL is a popular design entry language for FPGAs. Up until today, short verilog and vhdl questions have been tolerated in comp.arch.fpga. -- Mike Treseler

0 |

9/23/2009 10:11:54 PM

On Sep 23, 6:11=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > > On Sep 23, 7:56 pm, rickman <gnu...@gmail.com> wrote: > >> I was looking up the shift operator in VHDL since I seldom use it and > >> saw that there is both a shift left logical and a shift left > >> arithmetic. =A0The logic shift left shifts in zeros and the arithmetic > >> shift left shifts in the value of the lsb. > > sla shifts left and copies the right bit. > > Use of sla and sll on std_logic_vector is depreciated since > numeric_standard.shift_left automatically does the > "right thing" with the edge bits for signed or unsigned types. > > Antti.Luk...@googlemail.com wrote: > > how is this related to FPGA? > > VHDL is a popular design entry language for FPGAs. > Up until today, short verilog and vhdl questions > have been tolerated in comp.arch.fpga. Actually, my question is not about VHDL, it is about the utility of a left shift operator that copies the lsb. Or perhaps I should say the rightmost bit. As HK pointed out, the right bit and the lsb are not always synonymous. So I guess that answers my question of why this operator might be used. I have a bias for lsb being the "right hand" bit as well as the zeroth bit. I remember working with CDC documentation that used 0 to label the msb (on the left). That was the first time I had seen bits numbered that way and thought these guys must be pretty strange. I still have not seen an explanation of why that convention would be adopted, but then the limeys all drive on the left too! So go figure! I would suggest that FPGAs enforce rightmost bits being the lsb as well as labeled with a 0. That can be done in hardware, right? ;^) But you suggest that I should use instead the numeric standard function shift_left as it does the "right thing" for both types of operands. I see that there is little difference between shift_left and sll. function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a shift-left on an UNSIGNED vector COUNT times. -- The vacated positions are filled with '0'. -- The COUNT leftmost elements are lost. function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0) -- Result: Performs a shift-left on a SIGNED vector COUNT times. -- The vacated positions are filled with '0'. -- The COUNT leftmost elements are lost. It seems to be that they are doing the same thing... In fact, the one difference you might expect if you were using a singed operand is to not clobber the sign bit, but that is not prevented. So I fail to see why shift_left would have been added to the standard. Again, I expect if they were adding a shift_right, they needed a shift_left to fill the hole. In contrast the right_shift operator does handle the sign bit. I think someone fell down on the job with this one... or maybe not. If the result of a left shift on a signed number changes the sign bit, it would be an overflow anyway. So I guess it's all good! Rick

0 |

9/24/2009 10:04:37 PM

rickman wrote: > It seems to be that they are doing the same thing... It depends on the type of arg: -- Id: S.1 function shift_left ( ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; -- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0) -- Result: Performs a shift-left on an UNSIGNED vector COUNT times. -- The vacated positions are filled with Bit '0'. -- The COUNT leftmost bits are lost. -- Id: S.3 function shift_left ( ARG: SIGNED; COUNT: NATURAL) return SIGNED; -- Result subtype: SIGNED (ARG'LENGTH-1 downto 0) -- Result: Performs a shift-left on a SIGNED vector COUNT times. -- All bits of ARG, except ARG'LEFT, are shifted left COUNT times. -- The vacated positions are filled with Bit '0'. -- The COUNT leftmost bits, except ARG'LEFT, are lost. ----------------

0 |

9/24/2009 10:28:39 PM

rickman <gnuarm@gmail.com> wrote: < On Sep 23, 6:11?pm, Mike Treseler <mtrese...@gmail.com> wrote: (snip) <> sla shifts left and copies the right bit. (snip) < Actually, my question is not about VHDL, it is about the utility of a < left shift operator that copies the lsb. Or perhaps I should say the < rightmost bit. I do agree that is unusual, at least as an arithmetic operation. < As HK pointed out, the right bit and the lsb are not < always synonymous. So I guess that answers my question of why this < operator might be used. I have a bias for lsb being the "right hand" < bit as well as the zeroth bit. I only have verilog references, and have only written verilog. I can usually read VHDL, though. Verilog allows one to number the bits in either order. reg [3:0] i; reg [0:3] j; If you assign between such, the assignment is in left to right order, not in numerical order. < I remember working with CDC documentation that used 0 to label the msb < (on the left). That was the first time I had seen bits numbered that < way and thought these guys must be pretty strange. I still have not < seen an explanation of why that convention would be adopted, but then < the limeys all drive on the left too! So go figure! IBM S/360 and successor (and probably predecessors) numbers the MSB as bit 0. That is consistent with big endian byte order. (Some IBM processors were pretty much bit addressable, so that could have been important. S/360 is not, so the convention is only in the documentation.) It made things interesting with the 64 bit extension of z/Architecture. 32 bit instructions operate on the low half of the 64 bit registers, now bits 32 to 63. < I would suggest that FPGAs enforce rightmost bits being the lsb as < well as labeled with a 0. That can be done in hardware, right? ;^) That is a strange comment. FPGAs don't enforce anything. One can number (or letter) the bits anyway one wants, the FPGA just supplying a collection of logic. I don't know about VHDL but, as I said, verilog does not force one convention or the other. -- glen

0 |

9/24/2009 10:32:06 PM

The VHDL numeric_std package does not force bit 0 = LSB. 'Left is always MSB. Not sure about the new fixed point types... Andy

0 |

9/24/2009 11:11:13 PM

rickman <gnuarm@gmail.com> wrote: > I remember working with CDC documentation that used 0 to label the msb > (on the left). That was the first time I had seen bits numbered that > way and thought these guys must be pretty strange. I still have not > seen an explanation of why that convention would be adopted, but then > the limeys all drive on the left too! So go figure! HP historically did this too with PA-RISC and earlier architectures. In a big-endian world it can vaguely make sense as everything is read from left to right with increasing addresses. Of course can anyone use the words "left" and "right" without at least considering that the whole thing is a bit mad really. G.

0 |

9/25/2009 12:15:40 AM

On Sep 24, 6:28=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > rickman wrote: > > It seems to be that they are doing the same thing... > > It depends on the type of arg: > > =A0 =A0 =A0-- Id: S.1 > =A0 =A0function shift_left =A0( =A0ARG: UNSIGNED; COUNT: NATURAL) return = UNSIGNED; > =A0 =A0 =A0 -- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0) > =A0 =A0 =A0 -- Result: Performs a shift-left on an UNSIGNED vector COUNT = times. > =A0 =A0 =A0 -- =A0 =A0 =A0 =A0 The vacated positions are filled with Bit = '0'. > =A0 =A0 =A0 -- The COUNT leftmost bits are lost. > > =A0 =A0 =A0 -- Id: S.3 > =A0 =A0function shift_left =A0( =A0ARG: SIGNED; COUNT: NATURAL) return SI= GNED; > =A0 =A0 =A0 -- Result subtype: SIGNED (ARG'LENGTH-1 downto 0) > =A0 =A0 =A0 -- Result: Performs a shift-left on a SIGNED vector COUNT tim= es. > =A0 =A0 =A0 -- =A0 =A0All bits of ARG, except ARG'LEFT, are shifted left = COUNT times. > =A0 =A0 =A0 -- =A0 =A0 =A0 =A0 The vacated positions are filled with Bit = '0'. > =A0 =A0 =A0 -- =A0 =A0 =A0 =A0 The COUNT leftmost bits, except ARG'LEFT, = are lost. > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 ---------------- Why does your copy of this differ from mine? You snipped my quote of these functions, but they are very different. Still, the fact remains that it really doesn't matter. If you shift the entire number and the new value of the sign bit has changed, it was an overflow. Even if you don't shift the sign bit, it is still an overflow. I checked the file I read and it is dated 1995. I guess they redefined the signed left shift at some point. I wonder if that caused anyone any trouble??? Rick

0 |

9/25/2009 12:49:27 AM

On Sep 24, 6:32=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > rickman <gnu...@gmail.com> wrote: > > < I would suggest that FPGAs enforce rightmost bits being the lsb as > < well as labeled with a 0. =A0That can be done in hardware, right? =A0;^= ) > > That is a strange comment. =A0FPGAs don't enforce anything. =A0One can > number (or letter) the bits anyway one wants, the FPGA just supplying > a collection of logic. =A0I don't know about VHDL but, as I said, > verilog does not force one convention or the other. You clearly didn't see the smiley... Rick

0 |

9/25/2009 12:52:06 AM

On Sep 23, 5:47=A0pm, Herbert Kleebauer <k...@unibwm.de> wrote: > rickman wrote: > > That is what I was taught was the way to perform an arithmetic left > > shift, to fill the right positions with zero. =A0But this is also the > > logical left shift operation. =A0I don't understand why a left shift > > which fills the right most positions with the former lsb would be of > > value. =A0I suppose it could just exist to fill the space in a chart, > > but calling it an arithmetic left shift is a misnomer as arithmetic > > would use the same shift as the logical left shift. > > But only because you suppose that the MSB is on the left side > and the LSB on the right side. Yeah, I guess it also depends on which side you consider to be the right! Rick

0 |

9/25/2009 12:53:35 AM

On Thu, 24 Sep 2009 17:49:27 -0700 (PDT), rickman <gnuarm@gmail.com> wrote: >On Sep 24, 6:28�pm, Mike Treseler <mtrese...@gmail.com> wrote: >> rickman wrote: >> > It seems to be that they are doing the same thing... >> >> It depends on the type of arg: >> >> � � �-- Id: S.1 >> � �function shift_left �( �ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED; >> � � � -- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0) >> � � � -- Result: Performs a shift-left on an UNSIGNED vector COUNT times. >> � � � -- � � � � The vacated positions are filled with Bit '0'. >> � � � -- The COUNT leftmost bits are lost. >> >> � � � -- Id: S.3 >> � �function shift_left �( �ARG: SIGNED; COUNT: NATURAL) return SIGNED; >> � � � -- Result subtype: SIGNED (ARG'LENGTH-1 downto 0) >> � � � -- Result: Performs a shift-left on a SIGNED vector COUNT times. >> � � � -- � �All bits of ARG, except ARG'LEFT, are shifted left COUNT times. >> � � � -- � � � � The vacated positions are filled with Bit '0'. >> � � � -- � � � � The COUNT leftmost bits, except ARG'LEFT, are lost. >> � � � � � � � � � � � � � � � � � � � � � ---------------- > >Why does your copy of this differ from mine? You snipped my quote of >these functions, but they are very different. Still, the fact remains >that it really doesn't matter. If you shift the entire number and the >new value of the sign bit has changed, it was an overflow. Even if >you don't shift the sign bit, it is still an overflow. > >I checked the file I read and it is dated 1995. I guess they >redefined the signed left shift at some point. I wonder if that >caused anyone any trouble??? Or was it a documentation error of the cut/paste variety, later corrected? I would think this more likely than an actual change in behaviour. If you look at the associated package body (usually a second file) the source code should make it clear what the function really does. - Brian

0 |

9/25/2009 10:10:39 AM

rickman wrote: > You snipped my quote of > these functions, but they are very different. This is the package declaration. The code is in the package body.

0 |

9/25/2009 5:51:33 PM

On Thu, 24 Sep 2009 16:11:13 -0700 (PDT), Andy wrote: >The VHDL numeric_std package does not force bit 0 = LSB. 'Left is >always MSB. Just like Verilog, yes. >Not sure about the new fixed point types... You can declare them any way you like, but as soon as one of the overloaded operators gets its hands on a fixed-point operand it will throw an assertion error if the subscript range is ascending. So the package effectively enforces the rather reasonable convention that bit number N has place-value 2**N. Verilog can't do that. One up to VHDL, and one of several reasons why (as discussed elsewhere) I regard VHDL as a superior language to Verilog for RTL design (personal opinion only, of course). -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

0 |

9/25/2009 9:23:05 PM

On Sep 25, 1:51=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > rickman wrote: > > You snipped my quote of > > these functions, but they are very different. > > This is the package declaration. > The code is in the package body. Yes, but they are the documentation. I looked at the bodies, and in the copy I have, dated 1995, the bodies agree with the declaration comments. So it would seem that the functionality of shift_left for signed values changed at some point. I don't know when this package was adopted, so 1995 may be before it was official. But I suspect not. Rick

0 |

9/26/2009 3:32:20 PM

Hello, I think these two functions will come in very handy to solving the "write longword bits" problem. ShiftLeft( Left, Right, Shift ) ShiftRight( Right, Left, Shift ) Shifting with extra inputs is what is required to solve it nicely. // Begin of Code *** program Project1; {$APPTYPE CONSOLE} { Skybuck presents ShiftLeft( Left, Right, Shift ) and ShiftRight( Right, Left, Shift ) version 0.01 created on 5 may 2008 by Skybuck Flying. Be carefull though, the shift parameter must be 0 to 31. } uses SysUtils; // make overloaded versions for easy coding // display in big e...

Hello, Is there any command to shift left or right a vector ? thanks for your reply. patrice: <SNIP ...Is there any command to shift left or right a vector... a hint: help circshift us Try these: 4.1 Vectors To shift and rotate the elements of a vector, use X([ end 1:end-1 ]); % shift right/down 1 element X([ end-k+1:end 1:end-k ]); % shift right/down k elements X([ 2:end 1 ]); % shift left/up 1 element X([ k+1:end 1:k ]); % shift left/up k elements Try this link: <http://www.cs.huji.ac.il/course/2003/impr/matlab/MatlabTip.pdf> -TRO patrice wrote: > > > H...

Well, I know about shift up-and-down: shift-right ("red" or whatever) up and down on choose-box, HIST, things like that, take the cursor all the way to the beginning or the end. shift-left ("white") on up and down scroll the screen-full up or down (the FIRST such click *stupidly* goes to the final CURRENTLY-ON-SCREEN choice or whatever (meaning TWO double-button-pushes to scroll-down that FIRST time.) What are some of the OTHER possibilities, ie with the left and right arrows? Oh, apparantely undocumented, I&#...

Hi, Is there any way to catch the losing bit occurring due to Right Shift Operator ? e.g int a = 5 ; a = a >> 1 ; // // a is now 2 and the least significant bit is lost // // I want this solution for the question: "How to find if the number is even or odd using only "<<" or/and ">>" operators ?" On Thu, 29 Nov 2006, Santosh Nayak wrote: > > Is there any way to catch the losing bit occurring due to Right Shift > Operator ? int a = 5; int lost_bit = a & 1; a = a >> 1; /* now lost_bit holds the lost bit */ > ...

I have a problem where I have to do left shift and right shift. Long N; int shiftby; output = N >> shiftby; Above N is shifted right. Example if N=11101101 [binary value] will become: 1110110 when shiftby=1; will become: 0111011 when shiftby=2; will become: 0011101 when shiftby=3; will become: 0001110 when shiftby=4; will become: 0000111 when shiftby=5; will become: 0000011 when shiftby=6; will become: 0000001 when shiftby=7; When I want to shift left I can use output = N << shiftby; //[Not change in sign "<<" instead of ">>"] Above N is shi...

Hello, for the following code: unsigned int var = 0xFF2277F0UL; unsigned char take2 = (var << 8) >> 24; Is there any pitfall about the shift? (get '22' i.e. 34 or '"' as wanted) Thanks and best regards, Wenjie On 11 Jul 2003 04:07:43 -0700, gokkog@yahoo.com (Wenjie) wrote: >Hello, for the following code: > unsigned int var = 0xFF2277F0UL; > unsigned char take2 = (var << 8) >> 24; >Is there any pitfall about the shift? (get '22' i.e. 34 or '"' as wanted) It looks OK to me... -- Bob Hairg...

Is there a way to distinguish the SelectionType property in a figure for a Shift - click left and Shift - click right? Both result in the SelectionType 'Extend'... Thx "Stefan" <s@m.de> wrote in message <hpkik9$5c3$1@fred.mathworks.com>... > Is there a way to distinguish the SelectionType property in a figure for a Shift - click left and Shift - click right? > Both result in the SelectionType 'Extend'... > > Thx Hi Stefan, if you are in a callback function you can use this example with small changes, taken from the figure prope...

Hi, how is this code working? As per me since aNum is int8 so left shifting aNum by 8 would make it zero, how is it maintaining this? if i left shift it by 32 it becomes zero? unsigned __int8 aNum = 5; printf("%d",aNum << 16); Thanks Keshav -- [ See http://www.gotw.ca/resources/clcm.htm for info about ] [ comp.lang.c++.moderated. First time posters: Do this! ] Keshav wrote: > Hi, > how is this code working? As per me since aNum is int8 so left > shifting aNum by 8 would make it zero, how is it maintaining this? > if i left shift i...

hello every one in modelsim 10.0c i wrote >>> i mean shift arithmetic but the modelsim doesn't know. the second and third > are blue but the first > is black help me how can write shift arithmetic in modelsim. thanks Hi A.H.E.J. > i mean shift arithmetic but the modelsim doesn't know. It is not a tool matter but a language matter. I can help you but holistically not specifically. Can you send me a description of the entire problem? Please note that >>> denotes right rotation in some offshoot C-like languag= es. In Verilog there are 2 ...

Hi, in the header of my class I've a constant static const int a = ( 1 << 32 ) - 1; When compiling the code, g++ issues the warning "warning: left shift count >= width of type" Why? And how can I get rid of that? Thank you. Chris Christian Christmann wrote: > Hi, > > in the header of my class I've a constant > > static const int a = ( 1 << 32 ) - 1; > > When compiling the code, g++ issues the warning > "warning: left shift count >= width of type" > > Why? Because your implementation's representation of int ...

hii am relatively new to python..was checking out some bit shifting..when i do255<< 24 i get 4278190080whereas in java or c it gives -16777216can someone tell me why this is ?,what should i do if i want theoutput as -16777216 ?dnp:sI wrote a fn to show the binary digits in the number and it gives sameoutput for both numbers(4278190080 and -16777216)def pBinInt(str,i): print str,",int",i,", binary:" print " ", for j in range(31,-1,-1): if(((1 << j) & i) != 0): print 1, else: print 0, print "&...

Below is a snippet of code and the result (compiler version also mentioned). I fail to understand why the left shift operator behaves as if it were the left rotate operator when the operand is a variable. $ cat test.c #include <stdio.h> int main(void) { unsigned int a = 32, b = 33; printf("with constants 1 << 32 = %u, 1 << 33 = %u\n", 1<<32, 1<<33); printf("with variables 1 << 32 = %u, 1 << 33 = %u\n", 1<<a, 1<<b); return 0; } $ gcc test.c test.c: In function 'main': test.c:6:5: warning: left shi...

Hi all, How >>(right shift) and <<(left shift) 2'complement number (both positive and negative integer). Is x>>2 equal to floor(x/4)? And is x<<2 equal to x*4? Best regards, Davy Soho wrote: > Hi all, > > How >>(right shift) and <<(left shift) 2'complement number > (both positive and negative integer). > > Is x>>2 equal to floor(x/4)? > > And is x<<2 equal to x*4? > > Best regards, > Davy > Does bitshift: http://www.mathworks.com/access/helpdesk/help/techdoc/ref/bitshift.html do what you wa...

In C bitwise left shift operation invokes Undefined Behaviour when the left side operand has negative value. Relevant quote from ISO C99 (6.5.7/4) "The result of E1 << E2 is E1 left-shifted E2 bit positions; vacated bits are ﬁlled with zeros. If E1 has an unsigned type, the value of the result is E1× 2E2, reduced modulo one more than the maximum value representable in the result type. If E1 has a signed type and nonnegative value, and E1× 2E2 is representable in the result type, then that is the resulting value; otherwise, the behavior is undeﬁned." Bu...

... numbers , especially the properties of the traditional operations between them — addition , subtraction , multiplication and division . Arithmetic ...

... of numbers , especially the properties of the traditional operations between them— addition , subtraction , multiplication and division . Arithmetic ...

Get Arithmetic Invaders: Grade 2 Math Facts on the App Store. See screenshots and ratings, and read customer reviews.

Live coding of Ruby Quiz 7 - Arithmetic Puzzle "Countdown" Unscripted, unedited, (uncut) - Haskell Uncut Read more at my blog post: http://c ...

The deadliest man in Australia comes from Melbourne, but he is not a gangster or a hitman. He is more a foxtrotting man, these days. He can do ...

... is that numbers are wired into the human brain and perhaps a genetic anomaly explains why some children have severe difficulties with arithmetic. ...

... upgrade to Monster Math 2 Pro and get access to new worlds, more advanced reporting, and all of the math skills. Help your kids master arithmetic ...

MencalHD:Mental Arithmetic Training,Improve Your Skills In Math 1.0 Device: iOS iPad Only Category: Education Price: Free, Version: 1.0 ( iTunes ...

Pittsburgh Post-Gazette Analysis: Republicans' budget plans require creative arithmetic to add up Bellingham Herald WASHINGTON — Republicans ...

If only we weren't so frivolous , if we could get serious , maybe we could figure it all out.

Resources last updated: 1/24/2016 11:02:51 AM