I was looking up the shift operator in VHDL since I seldom use it and
saw that there is both a shift left logical and a shift left
arithmetic.  The logic shift left shifts in zeros and the arithmetic
shift left shifts in the value of the lsb.

I remember from school how a shift right can be logical or arithmetic
in order to implement signed and unsigned arithmetic.  But when
shifting left, I have always used a single shift operator, the logical
shift.

If an arithmetic left shift is used, it gives a valid result for some
values, assuming that the "valid" result is the same as multiplying by
2**n.  But the arithmetic left shift does not fit that model for other
values.  On the other hand, the logical left shift *always* returns a
value that is the 2**n multiple of the input value, assuming there are
no range issues such as overflowing into the sign bit.

So I don't understand the utility of the arithmetic left shift
operator and I especially don't see the reason for calling it
"arithmetic".  Can anyone shed some light on this?

Rick

On Sep 23, 7:56=A0pm, rickman <gnu...@gmail.com> wrote:
> I was looking up the shift operator in VHDL since I seldom use it and
> saw that there is both a shift left logical and a shift left
> arithmetic. =A0The logic shift left shifts in zeros and the arithmetic
> shift left shifts in the value of the lsb.
>
> I remember from school how a shift right can be logical or arithmetic
> in order to implement signed and unsigned arithmetic. =A0But when
> shifting left, I have always used a single shift operator, the logical
> shift.
>
> If an arithmetic left shift is used, it gives a valid result for some
> values, assuming that the "valid" result is the same as multiplying by
> 2**n. =A0But the arithmetic left shift does not fit that model for other
> values. =A0On the other hand, the logical left shift *always* returns a
> value that is the 2**n multiple of the input value, assuming there are
> no range issues such as overflowing into the sign bit.
>
> So I don't understand the utility of the arithmetic left shift
> operator and I especially don't see the reason for calling it
> "arithmetic". =A0Can anyone shed some light on this?
>
> Rick

how is this related to FPGA?
try vhdl newsgroup?

Antti

On Wed, 23 Sep 2009 09:59:57 -0700 (PDT), Antti wrote:

>how is this related to FPGA?
>try vhdl newsgroup?

Well... it is somewhat relevant.
And comp.lang.vhdl is being spammed
mercilessly right now by some bozo trying
to sell fake sneakers.  And Rick well knows
that many of the usual comp.lang.vhdl suspects
also hang out here.  So it's not so crazy.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

On Sep 23, 8:51=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Wed, 23 Sep 2009 09:59:57 -0700 (PDT), Antti wrote:
> >how is this related to FPGA?
> >try vhdl newsgroup?
>
> Well... it is somewhat relevant.
> And comp.lang.vhdl is being spammed
> mercilessly right now by some bozo trying
> to sell fake sneakers. =A0And Rick well knows
> that many of the usual comp.lang.vhdl suspects
> also hang out here. =A0So it's not so crazy.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

ic
comp . arch . embedded
is also sneaker victim

im not monitoring vhdl so wasnt aware its sneaker infection

ok, that valid excuse ;)

Antti

Antti.Lukats@googlemail.com <antti.lukats@googlemail.com> wrote:
< On Sep 23, 7:56?pm, rickman <gnu...@gmail.com> wrote:
<> I was looking up the shift operator in VHDL since I seldom use it and
<> saw that there is both a shift left logical and a shift left
<> arithmetic. ?The logic shift left shifts in zeros and the arithmetic
<> shift left shifts in the value of the lsb.

<> I remember from school how a shift right can be logical or arithmetic
<> in order to implement signed and unsigned arithmetic. ?But when
<> shifting left, I have always used a single shift operator, the logical
<> shift.
(snip)

<> So I don't understand the utility of the arithmetic left shift
<> operator and I especially don't see the reason for calling it
<> "arithmetic". ?Can anyone shed some light on this?

In software (languages such as C and Fortran) the difference is
in the possible consequence of overflow.  

Computing hardware does support arithmetic left shift:

http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/BOOKS/dz9zr003/7.5.116

such that the sign bit does not participate in the shift.  
 
< how is this related to FPGA?   try vhdl newsgroup?

For questions related to synthesis, it doesn't seem so far off
to post here.  For questions only related to simulation, or language
syntax questions, it does seem a little off topic.

In this case, I suppose it could be used in synthesis, but it
isn't so obvious.

-- glen

On Sep 23, 3:08=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> Antti.Luk...@googlemail.com <antti.luk...@googlemail.com> wrote:
>
> < On Sep 23, 7:56?pm, rickman <gnu...@gmail.com> wrote:
> <> I was looking up the shift operator in VHDL since I seldom use it and
> <> saw that there is both a shift left logical and a shift left
> <> arithmetic. ?The logic shift left shifts in zeros and the arithmetic
> <> shift left shifts in the value of the lsb.
>
> <> I remember from school how a shift right can be logical or arithmetic
> <> in order to implement signed and unsigned arithmetic. ?But when
> <> shifting left, I have always used a single shift operator, the logical
> <> shift.
> (snip)
>
> <> So I don't understand the utility of the arithmetic left shift
> <> operator and I especially don't see the reason for calling it
> <> "arithmetic". ?Can anyone shed some light on this?
>
> In software (languages such as C and Fortran) the difference is
> in the possible consequence of overflow. =A0
>
> Computing hardware does support arithmetic left shift:
>
> http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/BOOKS/dz9zr003/7.5.116
>
> such that the sign bit does not participate in the shift. =A0

Yes, but this is not an arithmetic left shift as defined by my
original post.

"For SLA or SLAG, zeros are supplied to the vacated bit positions on
the right"

That is what I was taught was the way to perform an arithmetic left
shift, to fill the right positions with zero.  But this is also the
logical left shift operation.  I don't understand why a left shift
which fills the right most positions with the former lsb would be of
value.  I suppose it could just exist to fill the space in a chart,
but calling it an arithmetic left shift is a misnomer as arithmetic
would use the same shift as the logical left shift.

To make Antti happy, ignore the use of the abbreviation VHDL in my
original post.  This is about an arithmetic algorithm as used in an
FPGA I am designing.

Rick

rickman wrote:

> That is what I was taught was the way to perform an arithmetic left
> shift, to fill the right positions with zero.  But this is also the
> logical left shift operation.  I don't understand why a left shift
> which fills the right most positions with the former lsb would be of
> value.  I suppose it could just exist to fill the space in a chart,
> but calling it an arithmetic left shift is a misnomer as arithmetic
> would use the same shift as the logical left shift.

But only because you suppose that the MSB is on the left side
and the LSB on the right side.

> On Sep 23, 7:56 pm, rickman <gnu...@gmail.com> wrote:

>> I was looking up the shift operator in VHDL since I seldom use it and
>> saw that there is both a shift left logical and a shift left
>> arithmetic.  The logic shift left shifts in zeros and the arithmetic
>> shift left shifts in the value of the lsb.

sla shifts left and copies the right bit.

Use of sla and sll on std_logic_vector is depreciated since
numeric_standard.shift_left automatically does the
"right thing" with the edge bits for signed or unsigned types.


Antti.Lukats@googlemail.com wrote:
> how is this related to FPGA?

VHDL is a popular design entry language for FPGAs.
Up until today, short verilog and vhdl questions
have been tolerated in comp.arch.fpga.

        -- Mike Treseler

On Sep 23, 6:11=A0pm, Mike Treseler <mtrese...@gmail.com> wrote:
> > On Sep 23, 7:56 pm, rickman <gnu...@gmail.com> wrote:
> >> I was looking up the shift operator in VHDL since I seldom use it and
> >> saw that there is both a shift left logical and a shift left
> >> arithmetic. =A0The logic shift left shifts in zeros and the arithmetic
> >> shift left shifts in the value of the lsb.
>
> sla shifts left and copies the right bit.
>
> Use of sla and sll on std_logic_vector is depreciated since
> numeric_standard.shift_left automatically does the
> "right thing" with the edge bits for signed or unsigned types.
>
> Antti.Luk...@googlemail.com wrote:
> > how is this related to FPGA?
>
> VHDL is a popular design entry language for FPGAs.
> Up until today, short verilog and vhdl questions
> have been tolerated in comp.arch.fpga.

Actually, my question is not about VHDL, it is about the utility of a
left shift operator that copies the lsb.  Or perhaps I should say the
rightmost bit.  As HK pointed out, the right bit and the lsb are not
always synonymous.  So I guess that answers my question of why this
operator might be used.  I have a bias for lsb being the "right hand"
bit as well as the zeroth bit.

I remember working with CDC documentation that used 0 to label the msb
(on the left).  That was the first time I had seen bits numbered that
way and thought these guys must be pretty strange.  I still have not
seen an explanation of why that convention would be adopted, but then
the limeys all drive on the left too!  So go figure!

I would suggest that FPGAs enforce rightmost bits being the lsb as
well as labeled with a 0.  That can be done in hardware, right?  ;^)

But you suggest that I should use instead the numeric standard
function shift_left as it does  the "right thing" for both types of
operands.  I see that there is little difference between shift_left
and sll.

  function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
  -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
  -- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
  --         The vacated positions are filled with '0'.
  --         The COUNT leftmost elements are lost.

  function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
  -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
  -- Result: Performs a shift-left on a SIGNED vector COUNT times.
  --         The vacated positions are filled with '0'.
  --         The COUNT leftmost elements are lost.


It seems to be that they are doing the same thing...  In fact, the one
difference you might expect if you were using a singed operand is to
not clobber the sign bit, but that is not prevented.  So I fail to see
why shift_left would have been added to the standard.  Again, I expect
if they were adding a shift_right, they needed a shift_left to fill
the hole.  In contrast the right_shift operator does handle the sign
bit.  I think someone fell down on the job with this one... or maybe
not.  If the result of a left shift on a signed number changes the
sign bit, it would be an overflow anyway.  So I guess it's all good!

Rick

rickman wrote:

> It seems to be that they are doing the same thing...

It depends on the type of arg:

     -- Id: S.1
   function shift_left  (  ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
      -- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0)
      -- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
      --         The vacated positions are filled with Bit '0'.
      -- The COUNT leftmost bits are lost.



      -- Id: S.3
   function shift_left  (  ARG: SIGNED; COUNT: NATURAL) return SIGNED;
      -- Result subtype: SIGNED (ARG'LENGTH-1 downto 0)
      -- Result: Performs a shift-left on a SIGNED vector COUNT times.
      --    All bits of ARG, except ARG'LEFT, are shifted left COUNT times.
      --         The vacated positions are filled with Bit '0'.
      --         The COUNT leftmost bits, except ARG'LEFT, are lost.
                                          ----------------

rickman <gnuarm@gmail.com> wrote:
< On Sep 23, 6:11?pm, Mike Treseler <mtrese...@gmail.com> wrote:
(snip)

<> sla shifts left and copies the right bit.
(snip) 

< Actually, my question is not about VHDL, it is about the utility of a
< left shift operator that copies the lsb.  Or perhaps I should say the
< rightmost bit.  

I do agree that is unusual, at least as an arithmetic operation.

< As HK pointed out, the right bit and the lsb are not
< always synonymous.  So I guess that answers my question of why this
< operator might be used.  I have a bias for lsb being the "right hand"
< bit as well as the zeroth bit.

I only have verilog references, and have only written verilog.
I can usually read VHDL, though.

Verilog allows one to number the bits in either order.

reg [3:0] i;
reg [0:3] j;

If you assign between such, the assignment is in left to
right order, not in numerical order.
 
< I remember working with CDC documentation that used 0 to label the msb
< (on the left).  That was the first time I had seen bits numbered that
< way and thought these guys must be pretty strange.  I still have not
< seen an explanation of why that convention would be adopted, but then
< the limeys all drive on the left too!  So go figure!

IBM S/360 and successor (and probably predecessors) numbers the
MSB as bit 0.  That is consistent with big endian byte order.
(Some IBM processors were pretty much bit addressable, so that
could have been important.  S/360 is not, so the convention is
only in the documentation.)  It made things interesting with the
64 bit extension of z/Architecture.  32 bit instructions operate
on the low half of the 64 bit registers, now bits 32 to 63.
 
< I would suggest that FPGAs enforce rightmost bits being the lsb as
< well as labeled with a 0.  That can be done in hardware, right?  ;^)

That is a strange comment.  FPGAs don't enforce anything.  One can
number (or letter) the bits anyway one wants, the FPGA just supplying
a collection of logic.  I don't know about VHDL but, as I said,
verilog does not force one convention or the other.

-- glen 

The VHDL numeric_std package does not force bit 0 = LSB. 'Left is
always MSB.

Not sure about the new fixed point types...

Andy

rickman <gnuarm@gmail.com> wrote:
> I remember working with CDC documentation that used 0 to label the msb
> (on the left).  That was the first time I had seen bits numbered that
> way and thought these guys must be pretty strange.  I still have not
> seen an explanation of why that convention would be adopted, but then
> the limeys all drive on the left too!  So go figure!

HP historically did this too with PA-RISC and earlier architectures.

In a big-endian world it can vaguely make sense as everything is read
from left to right with increasing addresses.

Of course can anyone use the words "left" and "right" without at
least considering that the whole thing is a bit mad really.

G.

On Sep 24, 6:28=A0pm, Mike Treseler <mtrese...@gmail.com> wrote:
> rickman wrote:
> > It seems to be that they are doing the same thing...
>
> It depends on the type of arg:
>
> =A0 =A0 =A0-- Id: S.1
> =A0 =A0function shift_left =A0( =A0ARG: UNSIGNED; COUNT: NATURAL) return =
UNSIGNED;
> =A0 =A0 =A0 -- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0)
> =A0 =A0 =A0 -- Result: Performs a shift-left on an UNSIGNED vector COUNT =
times.
> =A0 =A0 =A0 -- =A0 =A0 =A0 =A0 The vacated positions are filled with Bit =
'0'.
> =A0 =A0 =A0 -- The COUNT leftmost bits are lost.
>
> =A0 =A0 =A0 -- Id: S.3
> =A0 =A0function shift_left =A0( =A0ARG: SIGNED; COUNT: NATURAL) return SI=
GNED;
> =A0 =A0 =A0 -- Result subtype: SIGNED (ARG'LENGTH-1 downto 0)
> =A0 =A0 =A0 -- Result: Performs a shift-left on a SIGNED vector COUNT tim=
es.
> =A0 =A0 =A0 -- =A0 =A0All bits of ARG, except ARG'LEFT, are shifted left =
COUNT times.
> =A0 =A0 =A0 -- =A0 =A0 =A0 =A0 The vacated positions are filled with Bit =
'0'.
> =A0 =A0 =A0 -- =A0 =A0 =A0 =A0 The COUNT leftmost bits, except ARG'LEFT, =
are lost.
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 ----------------

Why does your copy of this differ from mine?  You snipped my quote of
these functions, but they are very different.  Still, the fact remains
that it really doesn't matter.  If you shift the entire number and the
new value of the sign bit has changed, it was an overflow.  Even if
you don't shift the sign bit, it is still an overflow.

I checked the file I read and it is dated 1995.  I guess they
redefined the signed left shift at some point.  I wonder if that
caused anyone any trouble???


Rick

On Sep 24, 6:32=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> rickman <gnu...@gmail.com> wrote:
>
> < I would suggest that FPGAs enforce rightmost bits being the lsb as
> < well as labeled with a 0. =A0That can be done in hardware, right? =A0;^=
)
>
> That is a strange comment. =A0FPGAs don't enforce anything. =A0One can
> number (or letter) the bits anyway one wants, the FPGA just supplying
> a collection of logic. =A0I don't know about VHDL but, as I said,
> verilog does not force one convention or the other.

You clearly didn't see the smiley...

Rick

On Sep 23, 5:47=A0pm, Herbert Kleebauer <k...@unibwm.de> wrote:
> rickman wrote:
> > That is what I was taught was the way to perform an arithmetic left
> > shift, to fill the right positions with zero. =A0But this is also the
> > logical left shift operation. =A0I don't understand why a left shift
> > which fills the right most positions with the former lsb would be of
> > value. =A0I suppose it could just exist to fill the space in a chart,
> > but calling it an arithmetic left shift is a misnomer as arithmetic
> > would use the same shift as the logical left shift.
>
> But only because you suppose that the MSB is on the left side
> and the LSB on the right side.

Yeah, I guess it also depends on which side you consider to be the
right!

Rick

On Thu, 24 Sep 2009 17:49:27 -0700 (PDT), rickman <gnuarm@gmail.com> wrote:

>On Sep 24, 6:28�pm, Mike Treseler <mtrese...@gmail.com> wrote:
>> rickman wrote:
>> > It seems to be that they are doing the same thing...
>>
>> It depends on the type of arg:
>>
>> � � �-- Id: S.1
>> � �function shift_left �( �ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
>> � � � -- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0)
>> � � � -- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
>> � � � -- � � � � The vacated positions are filled with Bit '0'.
>> � � � -- The COUNT leftmost bits are lost.
>>
>> � � � -- Id: S.3
>> � �function shift_left �( �ARG: SIGNED; COUNT: NATURAL) return SIGNED;
>> � � � -- Result subtype: SIGNED (ARG'LENGTH-1 downto 0)
>> � � � -- Result: Performs a shift-left on a SIGNED vector COUNT times.
>> � � � -- � �All bits of ARG, except ARG'LEFT, are shifted left COUNT times.
>> � � � -- � � � � The vacated positions are filled with Bit '0'.
>> � � � -- � � � � The COUNT leftmost bits, except ARG'LEFT, are lost.
>> � � � � � � � � � � � � � � � � � � � � � ----------------
>
>Why does your copy of this differ from mine?  You snipped my quote of
>these functions, but they are very different.  Still, the fact remains
>that it really doesn't matter.  If you shift the entire number and the
>new value of the sign bit has changed, it was an overflow.  Even if
>you don't shift the sign bit, it is still an overflow.
>
>I checked the file I read and it is dated 1995.  I guess they
>redefined the signed left shift at some point.  I wonder if that
>caused anyone any trouble???

Or was it a documentation error of the cut/paste variety, later corrected?
I would think this more likely than an actual change in behaviour.

If you look at the associated package body (usually a second file) the source
code should make it clear what the function really does.

- Brian

rickman wrote:

> You snipped my quote of
> these functions, but they are very different.

This is the package declaration.
The code is in the package body.

On Thu, 24 Sep 2009 16:11:13 -0700 (PDT), Andy wrote:

>The VHDL numeric_std package does not force bit 0 = LSB. 'Left is
>always MSB.

Just like Verilog, yes.

>Not sure about the new fixed point types...

You can declare them any way you like, but as soon
as one of the overloaded operators gets its hands on
a fixed-point operand it will throw an assertion error 
if the subscript range is ascending.  So the package 
effectively enforces the rather reasonable convention 
that bit number N has place-value 2**N.

Verilog can't do that.  One up to VHDL, and one of
several reasons why (as discussed elsewhere) I regard
VHDL as a superior language to Verilog for RTL design
(personal opinion only, of course).
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

On Sep 25, 1:51=A0pm, Mike Treseler <mtrese...@gmail.com> wrote:
> rickman wrote:
> > You snipped my quote of
> > these functions, but they are very different.
>
> This is the package declaration.
> The code is in the package body.

Yes, but they are the documentation.  I looked at the bodies, and in
the copy I have, dated 1995, the bodies agree with the declaration
comments.  So it would seem that the functionality of shift_left for
signed values changed at some point.  I don't know when this package
was adopted, so 1995 may be before it was official.  But I suspect
not.

Rick