I am working on a project that is taking a clock and inerfacing it with 
PLL to get a set of variable clock divisions. I am using the digilent s
board as a devolopment tool, and have been getting caught up on how to us
the expansion ports as generic I/O pins to output the clk signals to test
I assign output and input ports to the FPGA pins that match up to th
expansion port pins through the ucf. But the waveform I keep getting ou
of the pins are all the same. Even the VCC and ground pins output thi
bizzare waveform. Am I missing an enable pin somehwere on the board or d
I need to power up the ports? Or is there another way to output test cl
signals somewhere on the board? Any help would be much appreciated.  

"Renniks" <jks2999@rit.edu> schrieb im Newsbeitrag 
news:r7SdnXIbMPRQDjTenZ2dnUVZ_vmdnZ2d@giganews.com...
>I am working on a project that is taking a clock and inerfacing it with a
> PLL to get a set of variable clock divisions. I am using the digilent s3
> board as a devolopment tool, and have been getting caught up on how to use
> the expansion ports as generic I/O pins to output the clk signals to test.
> I assign output and input ports to the FPGA pins that match up to the
> expansion port pins through the ucf. But the waveform I keep getting out
> of the pins are all the same. Even the VCC and ground pins output this
> bizzare waveform. Am I missing an enable pin somehwere on the board or do
> I need to power up the ports? Or is there another way to output test clk
> signals somewhere on the board? Any help would be much appreciated.
>
>

you can probably measure the same waveform on your finger too?

try connecting ground to your measuring equipment, then there should
not be any more large noise on the ground pin.

the ports need to be configured as outputs and VCC IO in those
banks need to be present, that all what is needed to output an signal

Antti