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Spartan 3E starter kit DDR SDRAM

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I am relying to the older "Spartan 3E starter kit DDR SDRAM code
Options" thread.

Is there such a demo out, mentioned in the thread?

I read in several groups that it is a problem to get this DDR Ram
running ?
0
Reply fpgaengineerfrankfurt (16) 8/2/2007 10:53:16 PM 

On Aug 2, 3:53 pm, fpgauser <fpgaengineerfrankf...@arcor.de> wrote:
> I am relying to the older "Spartan 3E starter kit DDR SDRAM code
> Options" thread.
>
> Is there such a demo out, mentioned in the thread?
>
> I read in several groups that it is a problem to get this DDR Ram
> running ?

I'm not sure what you're refering to, but David Ashley ported the
OpenCore DDR SDRAM controller to the Spartan-3E500 start kit and
posted it here. I only had to adjust the .ucf file a bit to get it on
the Spartan-3E1600 Starter kit.

Tommy
0
Reply Tommy 8/2/2007 11:29:37 PM 


I should probably add: More information on MIG can be found on the
Memory Corner on xilinx.com:
http://www.xilinx.com/products/design_resources/mem_corner/
0
Reply jacobusn 8/3/2007 9:55:23 AM 

On Aug 3, 10:55 am, "jacob...@xilinx.com" <naude.j...@gmail.com>
wrote:
> I should probably add: More information on MIG can be found on the
> Memory Corner on xilinx.com:http://www.xilinx.com/products/design_resources/mem_corner/

Looks like my first message was not posted correctly: The Xilinx
Memory Interface Generator (MIG) generates ready-to-use HDL for the
Spartan-3E Startker Kit.

Cheers,
Jaco
0
Reply jacobusn 8/3/2007 10:06:00 AM 

Aha! So two chances to get a controller. Will try this ! Thanks to
both of you!
0
Reply fpgauser 8/4/2007 3:30:36 PM 

> The Xilinx
> Memory Interface Generator (MIG) generates ready-to-use HDL for the
> Spartan-3E Startker Kit.

I downloaded the reference design but did only find verilog files
which i cannot use. the re also ssems to be an ngc file missing, which
is nowhere in the zip archiv.

Isn't there a working project for ISE 8/9 which directly compiles and
produces some test ?

----

Concerning the other design: I found the .../dash/ocddr design. This
is one file, which I do not know how to handle. I  had been able to
seperate the files, but appart from the fact, that there is a reset
module missing, (and a debris of a vga module) I do not know how to
start with it and where. ISE imports it an dshows the hirarchy but
this is all.

---
0
Reply fpgauser 8/4/2007 11:25:36 PM
comp.arch.fpga 18335 articles. 19 followers.

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