Hello everyone, 

I'm trying to synthesise my design using Synplify Pro D-2010, but I am new
to this tool and encountering various problems. Here's my first one, which
I'd like to solve to be able to investigate other mysterious errors I'm
getting. 

In my design, I use a package called "types_viterbi". In my VHDL files, I
access this package by using the classic "use work.types_viterbi.all" line
of code. The file containing this package is added to my Synplify project.
I see it under the VHDL folder in the GUI shown when accessing my .prj
file. 

Except, when I try to do a "Synthax Check" or a "Synthesis Check" of my
components, Synplify returns a warning saying it cannot find
"types_viterbi". So, of course, it cannot find the constants I've declared
in this package, which is the error shown below. Here's the exact warning &
error returned by Synplify: 


@W: CD643
:"U:\Recherche\Algo_Viterbi_Parallele\VHDL\Synplify\source\decodeur_viterbi_carre.vhd":11:21:11:21|Ignoring
use clause - types_viterbi not found ... 
@E: CD255
:"U:\Recherche\Algo_Viterbi_Parallele\VHDL\Synplify\source\decodeur_viterbi_carre.vhd":15:42:15:42|No
identifier "poids_size" in scope 



I've read the documentation related to the compiler warning CD643, and it
says nothing about user-defined packages. However, in the Synplify
documentation on Libraries and Package, there's the following information :



If you create your own package and compile it into the work library to
access its definitions, you still need a use clause before the entity using
them, but not a library clause (because work is the default library.) 
To access packages other than those in work and std, you must provide a
library and use clause for each package as shown in the following example
of creating a resource library. 



Is there a step I must do to compile my package into the work library? I've
tried selecting the "types_viterbi.vhd" file and running the "Compile
Only/F7" command, but this compiles the top_level entity. I did another
Check Syntax of the top level entity after, and I still got the warning &
error. Yet, the compile command worked!  I haven't tried compiling my
package into a separate library. It would involve changing all of my VHDL
files to include this new library and I'd rather just have access to my
package from the work library. 

Any help clarifying this problem is welcomed. Again, I'm new to this tool,
so it may be a very simple solution, but I can't find anything in their
documentation or on a Google search.

Sincerly,

Isabelle LaRoche
Université Laval 


	   
					
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Does it simulate OK?

Sometimes the files need to be added in correct order, i.e.
the file with the package must be added before any library
units that make use of it. IIRC you can drag them around in the
gui to alter the order, or check the .prj file which should have
lines such as:
add_file -lib work my_pkg.vhd
add_file -lib work my_ent.vhd
etc.

HTH -- Pontus

>Does it simulate OK?
>
>Sometimes the files need to be added in correct order, i.e.
>the file with the package must be added before any library
>units that make use of it. IIRC you can drag them around in the
>gui to alter the order, or check the .prj file which should have
>lines such as:
>add_file -lib work my_pkg.vhd
>add_file -lib work my_ent.vhd
>etc.
>
>HTH -- Pontus
>

Hi,

thanks for the answer. 

It simulates fine in Modelsim. It synthesises fine in Xilinx ISE. In
Synplify, when I click "Run", it works fine until the Mapper process where
another error happens. I've been wanting to run a Syntax and Synthesis
check to investigate that error.

I've moved my package up the list of files so it's the first one, and the
error still happens. I've also ran the Compile Only (F7) option and it
works fine! It even says that the synthax has been run successfully! Here
are the logs for both options.

Synthax Check : 


@N: CD720 :"C:\Synopsys\fpga_D201003\lib\vhd\std.vhd":123:18:123:21|Setting
time resolution to ns
@I::
"U:\Recherche\Algo_Viterbi_Parallele\VHDL\Synplify\source\decodeur_viterbi_carre.vhd"
@W: CD643
:"U:\Recherche\Algo_Viterbi_Parallele\VHDL\Synplify\source\decodeur_viterbi_carre.vhd":10:26:10:26|Ignoring
use clause - types_viterbi not found ...
@E: CD255
:"U:\Recherche\Algo_Viterbi_Parallele\VHDL\Synplify\source\decodeur_viterbi_carre.vhd":14:42:14:42|No
identifier "poids_size" in scope

Compile Only : 


@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : decodeur_viterbi_carre.vhd(13) | Top entity is set to
decodeur_viterbi_carre.
VHDL syntax check successful!


I'm at a loss as to what is causing the Synthax Check to fail. I'll
continue to tinker with the different options and processes, but any
further help/info would be appreciated.

Isabelle LaRoche
Université Laval
Québec, Qc, Canada	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Could you try to introduce an error in the package declaration,
just to see that the compiler/analyzer is actually looking
at the file you think its looking at?!?
-- Pontus

>Could you try to introduce an error in the package declaration,
>just to see that the compiler/analyzer is actually looking
>at the file you think its looking at?!?
>-- Pontus
>

I removed a ";" at the end of a constant declaration in the package. The
"Compile Only" process that I ran on my entity found the error in the
package. 	   
					
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Posted through http://www.FPGARelated.com