Hi,
when i do post route simulation i get a bunch of error similar to the
following
 ** Error:
F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup(
negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849 ps,
520 ps );
#    Time: 106849 ps  Iteration: 0  Instance: /test_v/uut/v_ram_addr_4
# ** Error:
F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup(
negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849 ps,
520 ps );
#    Time: 106849 ps  Iteration: 0  Instance: /test_v/uut/v_ram_addr_1
# ** Error:
F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup(
negedge SRST &&& (srst_clk_enable1 == 1):106398 ps, posedge CLK:106849 ps,
520 ps );
#    Time: 106849 ps  Iteration: 0  Instance: /test_v/uut/v_ram_addr_2
# ** Error:
F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup(
negedge SRST &&& (srst_clk_enable1 == 1):106398 ps, posedge CLK:106849 ps,
520 ps );
#    Time: 106849 ps  Iteration: 0  Instance: /test_v/uut/v_ram_addr_3

   who can tell me how to correct these errors??	   
					
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>Hi,
>when i do post route simulation i get a bunch of error similar to the
>following

> ** Error:
>F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup(
>negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849
ps,
>520 ps );
>#    Time: 106849 ps  Iteration: 0  Instance: /test_v/uut/v_ram_addr_4


>   who can tell me how to correct these errors??	   
>					
>---------------------------------------		
>This message was sent using the comp.arch.fpga web interface on
>http://www.FPGARelated.com
>

This error tells you that when you remove your reset signal that the flip
flops see it 520 ps before the next rising edge of the clock and that this
is not enough time if you wanted to change the flops value on that first
clock. You need to redesign your reset distribution to ensure that it meets
timing.

	   
					
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>>Hi,
>>when i do post route simulation i get a bunch of error similar to the
>>following
>
>> ** Error:
>>F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890):
$setup(
>>negedge SRST &&& (srst_clk_enable1 == 1):106333 ps, posedge CLK:106849
>ps,
>>520 ps );
>>#    Time: 106849 ps  Iteration: 0  Instance: /test_v/uut/v_ram_addr_4
>
>
>>   who can tell me how to correct these errors??	   
>>					
>>---------------------------------------		
>>This message was sent using the comp.arch.fpga web interface on
>>http://www.FPGARelated.com
>>
>
>This error tells you that when you remove your reset signal that the flip
>flops see it 520 ps before the next rising edge of the clock and that
this
>is not enough time if you wanted to change the flops value on that first
>clock. You need to redesign your reset distribution to ensure that it
meets
>timing.
>thanks for your reply ,i have set the rst==1 in "initialize inputs" in my 
test.v .but there are aslo two errors .
  # .main_pane.signals.interior.cs
# ** Error:
F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(113485): $hold(
negedge CLK:447545 ps, negedge I &&& in_clk_enable1:447552 ps, 118 ps );
#    Time: 447552 ps  Iteration: 1  Instance: /test_v/uut/yuv_addr_1_1
# ** Error:
F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(113485): $hold(
negedge CLK:863545 ps, negedge I &&& in_clk_enable1:863552 ps, 118 ps );
#    Time: 863552 ps  Iteration: 1  Instance: /test_v/uut/yuv_addr_1_1

  ???????
>	   
>					
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>	   
					
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>>
>>This error tells you that when you remove your reset signal that the
flip
>>flops see it 520 ps before the next rising edge of the clock and that

Actually it needs to see it 520 ps before the clock but you only have 516
ps.
It is barely missing


>>thanks for your reply ,i have set the rst==1 in "initialize inputs" in my

>test.v .but there are aslo two errors .
>  # .main_pane.signals.interior.cs
># ** Error:
>F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(113485): $hold(
>negedge CLK:447545 ps, negedge I &&& in_clk_enable1:447552 ps, 118 ps );
>#    Time: 447552 ps  Iteration: 1  Instance: /test_v/uut/yuv_addr_1_1
># ** Error:
>F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(113485): $hold(
>negedge CLK:863545 ps, negedge I &&& in_clk_enable1:863552 ps, 118 ps );
>#    Time: 863552 ps  Iteration: 1  Instance: /test_v/uut/yuv_addr_1_1
>

These are hold time violations. You need to hold your inputs for 118 ps
after the clock edge but you are only seeing 7 ps. The inputs are chainging
to soon.



	   
					
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