Looking for interest in an Open Source Hardware USB programmable FPGA,
XC3S250E. I have been having some difficulty getting the right people
exposed to this project. If you have any interest in this project
would like to hear from you. It is headed into an Open Source Hardware
agreement therefore their is no proprietary information about the
design.

Here is an image of the board.
http://www.mediafire.com/imageview.php?quickkey=yhjjddznzmx&thumb=5

Cy Drollinger
Electronic Realization L.L.C.
313 W. Mendenhall #5
Bozeman, MT 59715
PH: 406-586-5502
Email: cy@montana.net

On Sep 22, 10:19=A0pm, nobody <cydrollin...@gmail.com> wrote:
> Looking for interest in an Open Source Hardware USB programmable FPGA,
> XC3S250E. I have been having some difficulty getting the right people
> exposed to this project. If you have any interest in this project
> would like to hear from you. It is headed into an Open Source Hardware
> agreement therefore their is no proprietary information about the
> design.
>
> Here is an image of the board.http://www.mediafire.com/imageview.php?quic=
kkey=3Dyhjjddznzmx&thumb=3D5
>
> Cy Drollinger
> Electronic Realization L.L.C.
> 313 W. Mendenhall #5
> Bozeman, MT 59715
> PH: 406-586-5502
> Email: c...@montana.net

Dear Cy

who are the right people?
customers buying the hardware from you?
an OEM fab that manufacturers the board for you cheaply?
developers who spend their time to support your board so you can use
those open source projects to sell more boards and make more money?
somebody who can give you good advice?

the PCB is far too expensive to make for "open source" guys, so nobody
will build this board, unless you manufacture and sell it cheaply,
so whatever you call open source hardware, it is just an commercial
products with schematic made public, but the schematics of most FPGA
development hardware is openly public anyway, so where is you point?

you really have to say what type of contacts you are looking for!

Antti

Antti,

I enjoy your responses they are to the bone, but valid. The right
people are engineers who wish to pick this project up for their
benefit, yes antti as well as mine. The engineer would be some one
willing to pay a bit extra for one of four boards available with all
the design file associated with the boards. These files are the meat
of the work and would allow an engineer to make changes from the
current form to one more suitable to their needs, if necessary. Open
Source license also allows anyone willing to manufacture this product
for sale and profit of their own, royalty free. Development and
testing is a huge cost and has been paid for in this project. Yes,
antti schematics are available for many of the development boards but
firmware and how things are implemented are not. Digilent for example
produced a project that only required a usb to miniB connection to the
board to program utilizing Xilinx's impact program, how did they do
that? They will not tell me, I understand, but it was worth asking.

If the 4 layer printed circuit board was manufactured for $6 is that
to expensive?

My point: is placing all of this projects work in an open source
license to be easily duplicated at a reasonable cost one board under
$50.00 for someone in need of well behaved electronic signals, maybe
an engineer, a student, a hobbyist, and the like. Antti, you are so
preceptive, Yes, I would like to be able to accept notes of
appreciation for this body of work, because someone finds it helpful.
Being able to discuss this body of work and let it go out to those who
would find it useful makes me smile. Open Source Hardware licensing
just prevents anyone from strangling the work and making it theirs,
plagiarism. This body of work is not quite original but is not a rip
off, or a copy of another work. Yes, their are similar projects out
there and I have asked for help on this project from those similar
project, but understandably I got go away, I did.
I have spent my resource on this project and I need more to continue
on or even try something different.

Thanks for asking Antti,

Cy Drollinger

nobody <cydrollinger@gmail.com> wrote:

>Looking for interest in an Open Source Hardware USB programmable FPGA,
>XC3S250E. I have been having some difficulty getting the right people
>exposed to this project. If you have any interest in this project
>would like to hear from you. It is headed into an Open Source Hardware
>agreement therefore their is no proprietary information about the
>design.
>
>Here is an image of the board.
>http://www.mediafire.com/imageview.php?quickkey=yhjjddznzmx&thumb=5

What is the purpose of the board? What needs to be done?

I see an FTDI chip. Can it be programmed through OpenOCD / serial port
JTAG?

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

On Sep 23, 6:58=A0pm, nobody <cydrollin...@gmail.com> wrote:
> Antti,
>
> I enjoy your responses they are to the bone, but valid. The right
> people are engineers who wish to pick this project up for their
> benefit, yes antti as well as mine. The engineer would be some one
> willing to pay a bit extra for one of four boards available with all
> the design file associated with the boards. These files are the meat
> of the work and would allow an engineer to make changes from the
> current form to one more suitable to their needs, if necessary. Open
> Source license also allows anyone willing to manufacture this product
> for sale and profit of their own, royalty free. Development and
> testing is a huge cost and has been paid for in this project. Yes,
> antti schematics are available for many of the development boards but
> firmware and how things are implemented are not. Digilent for example
> produced a project that only required a usb to miniB connection to the
> board to program utilizing Xilinx's impact program, how did they do
> that? They will not tell me, I understand, but it was worth asking.
>
> If the 4 layer printed circuit board was manufactured for $6 is that
> to expensive?
>
> My point: is placing all of this projects work in an open source
> license to be easily duplicated at a reasonable cost one board under
> $50.00 for someone in need of well behaved electronic signals, maybe
> an engineer, a student, a hobbyist, and the like. Antti, you are so
> preceptive, Yes, I would like to be able to accept notes of
> appreciation for this body of work, because someone finds it helpful.
> Being able to discuss this body of work and let it go out to those who
> would find it useful makes me smile. Open Source Hardware licensing
> just prevents anyone from strangling the work and making it theirs,
> plagiarism. This body of work is not quite original but is not a rip
> off, or a copy of another work. Yes, their are similar projects out
> there and I have asked for help on this project from those similar
> project, but understandably I got go away, I did.
> I have spent my resource on this project and I need more to continue
> on or even try something different.
>
> Thanks for asking Antti,
>
> Cy Drollinger

Cy

you havent done your homework ;)

1) Xilinx USB cable can be put on customer board (yours) the schematic
is FREELY available, FX2+CPLD, support:impact/chipscope/xmd
2) Digilent USB cable can put on customer board  (yours) the schematic
is FREELY available, FX2 only, support: chipscope/xmd

3) Anttis option:
a] FT232RL and S3E, CBUS used for CLK and JTAG, i can provide ALL
TOOLS needed for this
b] FT245RL + S3AN (uses multiboot)

a and b allow full programmability over usb, at lower cost then your,
and lower than digilent or xilinx usb embedded

all solutions are EASY and READY for anyone to benefit, and lower cost
then yours

6$ one off 4 layer PCB? you have good fab, if so!

but, you use hard to get and hard to use connectors, making also add
on boards expensive, so that reduces the interest another level

your work is 1:1 same as "console FPGA" or have i failed to see
something?
i see nothing what your board does better (both designs are WAY TOO
OLD, and WAY too expensive...)

Antti

On Sep 23, 7:17=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
> nobody <cydrollin...@gmail.com> wrote:
> >Looking for interest in an Open Source Hardware USB programmable FPGA,
> >XC3S250E. I have been having some difficulty getting the right people
> >exposed to this project. If you have any interest in this project
> >would like to hear from you. It is headed into an Open Source Hardware
> >agreement therefore their is no proprietary information about the
> >design.
>
> >Here is an image of the board.
> >http://www.mediafire.com/imageview.php?quickkey=3Dyhjjddznzmx&thumb=3D5
>
> What is the purpose of the board? What needs to be done?
>
> I see an FTDI chip. Can it be programmed through OpenOCD / serial port
> JTAG?
>
> --
> Failure does not prove something is impossible, failure simply
> indicates you are not using the right tools...
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg=
er hammer!"
> --------------------------------------------------------------

NO

you need a JTAG cable to program the CPLD
then you can download the FPGA
much same idea as the ondemand thing

there is no "bootstrap" option that would
allow the board to be flashd with empty
CPLD and flash soldered =3D=3D=3D BAD design

Antti

On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote:
> Antti,
>
> I enjoy your responses they are to the bone, but valid. The right
> people are engineers who wish to pick this project up for their
> benefit, yes antti as well as mine. The engineer would be some one
> willing to pay a bit extra for one of four boards available with all
> the design file associated with the boards. These files are the meat
> of the work and would allow an engineer to make changes from the
> current form to one more suitable to their needs, if necessary. Open
> Source license also allows anyone willing to manufacture this product
> for sale and profit of their own, royalty free. Development and
> testing is a huge cost and has been paid for in this project. Yes,
> antti schematics are available for many of the development boards but
> firmware and how things are implemented are not. Digilent for example
> produced a project that only required a usb to miniB connection to the
> board to program utilizing Xilinx's impact program, how did they do
> that? They will not tell me, I understand, but it was worth asking.

Yes, there are vendors who do not make all of their design files
available for FPGA development boards.  But for the most part, the
FPGA makers provide development boards and make all of their design
files available.  I think they do this to reduce the amount of support
required.  If you have all of the design files, you don't need to ask
so many questions, you can just look it up yourself.  So in that
sense, there are a number of open source FPGA development boards.
Just not with the freedom to make your own copies although I can't
imagine an FPGA vendor would object since you would be putting their
parts on it!


> If the 4 layer printed circuit board was manufactured for $6 is that
> to expensive?

No one can have a board manufactured for $6.  You might be able to get
100 for $600 or possibly even 10 for $60, but not 1 for $6.  That is
one of the problems with open source hardware.  It is "hard" and often
difficult to make on your own.  But that does not need to be a
problem.  The most successful open source hardware (OSH) project I
have seen is the Beagle Board which can only be made in pretty
advanced factories.  It uses a Package on Package mounting technique
for the processor memory as the OMAP CPU used is intended for use in
PDAs and cell phone like applications.  So clearly, the fact that you
might have to sell some part or even all of the board would not doom
the project as Antti might think.  (Not trying to put words in your
mouth Antti, just making a point).

In fact, I am thinking about an open source GPS receiver project which
would require not only the electronic hardware, but also a mechanical
design be done.  Now *that* can be a problem for open source I
think.


> My point: is placing all of this projects work in an open source
> license to be easily duplicated at a reasonable cost one board under
> $50.00 for someone in need of well behaved electronic signals, maybe
> an engineer, a student, a hobbyist, and the like. Antti, you are so
> preceptive, Yes, I would like to be able to accept notes of
> appreciation for this body of work, because someone finds it helpful.
> Being able to discuss this body of work and let it go out to those who
> would find it useful makes me smile. Open Source Hardware licensing
> just prevents anyone from strangling the work and making it theirs,
> plagiarism. This body of work is not quite original but is not a rip
> off, or a copy of another work. Yes, their are similar projects out
> there and I have asked for help on this project from those similar
> project, but understandably I got go away, I did.
> I have spent my resource on this project and I need more to continue
> on or even try something different.

Have you defined your goals for this project?  If you are going to
succeed, you need to know what you are trying to do, *clearly*.
Others can give feedback on the goals and you can modify them to
include as many others as possible.  Then you will get as much support
as possible.

Rick

On Sep 23, 7:38=A0pm, rickman <gnu...@gmail.com> wrote:
> On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
>
>
> > Antti,
>
> > I enjoy your responses they are to the bone, but valid. The right
> > people are engineers who wish to pick this project up for their
> > benefit, yes antti as well as mine. The engineer would be some one
> > willing to pay a bit extra for one of four boards available with all
> > the design file associated with the boards. These files are the meat
> > of the work and would allow an engineer to make changes from the
> > current form to one more suitable to their needs, if necessary. Open
> > Source license also allows anyone willing to manufacture this product
> > for sale and profit of their own, royalty free. Development and
> > testing is a huge cost and has been paid for in this project. Yes,
> > antti schematics are available for many of the development boards but
> > firmware and how things are implemented are not. Digilent for example
> > produced a project that only required a usb to miniB connection to the
> > board to program utilizing Xilinx's impact program, how did they do
> > that? They will not tell me, I understand, but it was worth asking.
>
> Yes, there are vendors who do not make all of their design files
> available for FPGA development boards. =A0But for the most part, the
> FPGA makers provide development boards and make all of their design
> files available. =A0I think they do this to reduce the amount of support
> required. =A0If you have all of the design files, you don't need to ask
> so many questions, you can just look it up yourself. =A0So in that
> sense, there are a number of open source FPGA development boards.
> Just not with the freedom to make your own copies although I can't
> imagine an FPGA vendor would object since you would be putting their
> parts on it!
>
> > If the 4 layer printed circuit board was manufactured for $6 is that
> > to expensive?
>
> No one can have a board manufactured for $6. =A0You might be able to get
> 100 for $600 or possibly even 10 for $60, but not 1 for $6. =A0That is
> one of the problems with open source hardware. =A0It is "hard" and often
> difficult to make on your own. =A0But that does not need to be a
> problem. =A0The most successful open source hardware (OSH) project I
> have seen is the Beagle Board which can only be made in pretty
> advanced factories. =A0It uses a Package on Package mounting technique
> for the processor memory as the OMAP CPU used is intended for use in
> PDAs and cell phone like applications. =A0So clearly, the fact that you
> might have to sell some part or even all of the board would not doom
> the project as Antti might think. =A0(Not trying to put words in your
> mouth Antti, just making a point).
>
> In fact, I am thinking about an open source GPS receiver project which
> would require not only the electronic hardware, but also a mechanical
> design be done. =A0Now *that* can be a problem for open source I
> think.
>
> > My point: is placing all of this projects work in an open source
> > license to be easily duplicated at a reasonable cost one board under
> > $50.00 for someone in need of well behaved electronic signals, maybe
> > an engineer, a student, a hobbyist, and the like. Antti, you are so
> > preceptive, Yes, I would like to be able to accept notes of
> > appreciation for this body of work, because someone finds it helpful.
> > Being able to discuss this body of work and let it go out to those who
> > would find it useful makes me smile. Open Source Hardware licensing
> > just prevents anyone from strangling the work and making it theirs,
> > plagiarism. This body of work is not quite original but is not a rip
> > off, or a copy of another work. Yes, their are similar projects out
> > there and I have asked for help on this project from those similar
> > project, but understandably I got go away, I did.
> > I have spent my resource on this project and I need more to continue
> > on or even try something different.
>
> Have you defined your goals for this project? =A0If you are going to
> succeed, you need to know what you are trying to do, *clearly*.
> Others can give feedback on the goals and you can modify them to
> include as many others as possible. =A0Then you will get as much support
> as possible.
>
> Rick

Rick,

beagle is:
1) backed up by TI
2) uses (used) newest components

Cy's design:
1) uses OBSOLETED and NFND components

see the difference?

Cy: doing something different is an option

And as before i am failing to see what you expect to find?

I can only sayd that no "open source" developer will be
ordering and assembling those boards for personal use
and no company is interested to produce them either

so if somebody makes the boards its only you, and then
you have boards with 2 generation too old FPGA that
nobody is interested in, and that you can not sell even
for break even

Antti

Antti,

You have it all figured dont ya, Nobody, nothing, no company, no
interest. Well, seems as if two others have joined in to express some
interest.

 I agree the mating components, 4 connectors, used on the board for
stacking the boards are expensive and therefore need to rethink
that.

There is an SPI flash in the lower right hand of that picture, which I
have used to boot load, yes it was programmed with the Xilinx platform
Cable USB II and the impact software. I do believe that the hardware
is in place to allow a file to be copied into the flash through the
USB, CPLD, FPGA. Add power from a walwart and the FPGA is up and
running. I am not all together convinced that this can not become a
multiboot system, however it is not spoken about in either XAPP951 or
XAPP974.

Rick,

I did not see the problem for your electrical and mechanical designs
of the GPS receiver. When the design is done and all is working
clients merely order the mechanical component order the electrical
component put it together. If there is need for something different
all design file are available for the next design, who ever it may be.
Clear goals: Yes, agreed. I have met my initial goals: an operable usb
powered and programmable fpga with a couple of addition for usability.
Now what? Well as antti has so strongly points out no one wants this
thing. Well, i have it, I am in need of it, and I do not want to
purchase any of antti products, or anyone elses, for any of my
contracted work, not that I have alot. I need some help in putting
together something a bit more robust and engineering friendly,
friendly to me and future work. I do not want to put something
together that does everything just gets far enough along that I can
work on the customers specifics. I can not be the only one in this
situation, therefore I want to work with a group of like minded
engineers to establish a good off the shelf component for future use.
Now, I'm not selfish I would like to share and make all of it
available, I like what happened to audrino it is a nice little 16 bit
processor. FPGA's do not suffer this identity crisis, 8 bit 32 bit
processors or whatever the hardware can be reconfigured to be. I need
it and want it. This board is only to say that I have the ability is
anyone else interested, well, the internet is good enough to house a
loose collection of engineers for a small project.

Nico,
What yet needs to be done, that's easy just look over Antti posts and
wherever he says no, not, cant, doesnt, neight just solve those
problems. Just because antti says no, not, cant, doesnt, neight does
not make it so.

Anyways- thanks for taking time to post and give me some ideas.

Cy Drollinger

On Sep 23, 10:41=A0pm, nobody <cydrollin...@gmail.com> wrote:
> Antti,
>
> You have it all figured dont ya, Nobody, nothing, no company, no
> interest. Well, seems as if two others have joined in to express some
> interest.
>
> =A0I agree the mating components, 4 connectors, used on the board for
> stacking the boards are expensive and therefore need to rethink
> that.
>
> There is an SPI flash in the lower right hand of that picture, which I
> have used to boot load, yes it was programmed with the Xilinx platform
> Cable USB II and the impact software. I do believe that the hardware
> is in place to allow a file to be copied into the flash through the
> USB, CPLD, FPGA. Add power from a walwart and the FPGA is up and
> running. I am not all together convinced that this can not become a
> multiboot system, however it is not spoken about in either XAPP951 or
> XAPP974.
>
> Rick,
>
> I did not see the problem for your electrical and mechanical designs
> of the GPS receiver. When the design is done and all is working
> clients merely order the mechanical component order the electrical
> component put it together. If there is need for something different
> all design file are available for the next design, who ever it may be.
> Clear goals: Yes, agreed. I have met my initial goals: an operable usb
> powered and programmable fpga with a couple of addition for usability.
> Now what? Well as antti has so strongly points out no one wants this
> thing. Well, i have it, I am in need of it, and I do not want to
> purchase any of antti products, or anyone elses, for any of my
> contracted work, not that I have alot. I need some help in putting
> together something a bit more robust and engineering friendly,
> friendly to me and future work. I do not want to put something
> together that does everything just gets far enough along that I can
> work on the customers specifics. I can not be the only one in this
> situation, therefore I want to work with a group of like minded
> engineers to establish a good off the shelf component for future use.
> Now, I'm not selfish I would like to share and make all of it
> available, I like what happened to audrino it is a nice little 16 bit
> processor. FPGA's do not suffer this identity crisis, 8 bit 32 bit
> processors or whatever the hardware can be reconfigured to be. I need
> it and want it. This board is only to say that I have the ability is
> anyone else interested, well, the internet is good enough to house a
> loose collection of engineers for a small project.
>
> Nico,
> What yet needs to be done, that's easy just look over Antti posts and
> wherever he says no, not, cant, doesnt, neight just solve those
> problems. Just because antti says no, not, cant, doesnt, neight does
> not make it so.
>
> Anyways- thanks for taking time to post and give me some ideas.
>
> Cy Drollinger

there is no failsafe multiboot in S3E

just another reason never use something as old as S3E

Antti
PS I am not as negative just trying to help you,
and yes i have pretty much figured out

On Sep 23, 10:47=A0pm, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 23, 10:41=A0pm, nobody <cydrollin...@gmail.com> wrote:
>
>
>
> > Antti,
>
> > You have it all figured dont ya, Nobody, nothing, no company, no
> > interest. Well, seems as if two others have joined in to express some
> > interest.
>
> > =A0I agree the mating components, 4 connectors, used on the board for
> > stacking the boards are expensive and therefore need to rethink
> > that.
>
> > There is an SPI flash in the lower right hand of that picture, which I
> > have used to boot load, yes it was programmed with the Xilinx platform
> > Cable USB II and the impact software. I do believe that the hardware
> > is in place to allow a file to be copied into the flash through the
> > USB, CPLD, FPGA. Add power from a walwart and the FPGA is up and
> > running. I am not all together convinced that this can not become a
> > multiboot system, however it is not spoken about in either XAPP951 or
> > XAPP974.
>
> > Rick,
>
> > I did not see the problem for your electrical and mechanical designs
> > of the GPS receiver. When the design is done and all is working
> > clients merely order the mechanical component order the electrical
> > component put it together. If there is need for something different
> > all design file are available for the next design, who ever it may be.
> > Clear goals: Yes, agreed. I have met my initial goals: an operable usb
> > powered and programmable fpga with a couple of addition for usability.
> > Now what? Well as antti has so strongly points out no one wants this
> > thing. Well, i have it, I am in need of it, and I do not want to
> > purchase any of antti products, or anyone elses, for any of my
> > contracted work, not that I have alot. I need some help in putting
> > together something a bit more robust and engineering friendly,
> > friendly to me and future work. I do not want to put something
> > together that does everything just gets far enough along that I can
> > work on the customers specifics. I can not be the only one in this
> > situation, therefore I want to work with a group of like minded
> > engineers to establish a good off the shelf component for future use.
> > Now, I'm not selfish I would like to share and make all of it
> > available, I like what happened to audrino it is a nice little 16 bit
> > processor. FPGA's do not suffer this identity crisis, 8 bit 32 bit
> > processors or whatever the hardware can be reconfigured to be. I need
> > it and want it. This board is only to say that I have the ability is
> > anyone else interested, well, the internet is good enough to house a
> > loose collection of engineers for a small project.
>
> > Nico,
> > What yet needs to be done, that's easy just look over Antti posts and
> > wherever he says no, not, cant, doesnt, neight just solve those
> > problems. Just because antti says no, not, cant, doesnt, neight does
> > not make it so.
>
> > Anyways- thanks for taking time to post and give me some ideas.
>
> > Cy Drollinger
>
> there is no failsafe multiboot in S3E
>
> just another reason never use something as old as S3E
>
> Antti
> PS I am not as negative just trying to help you,
> and yes i have pretty much figured out

i must correct myself

s3e: no failsafe multiboot in SPI flash without external circuitry

Antti

Rick,

You were right, I can not refute you at this time it is $6.10 per
board so it stands no one can do it for $6 a board. Yes, they do a
minimum of $50.00. Still that seems good, no that seems great!

Cy

On Sep 24, 5:30=A0pm, nobody <cydrollin...@gmail.com> wrote:
> Rick,
>
> You were right, I can not refute you at this time it is $6.10 per
> board so it stands no one can do it for $6 a board. Yes, they do a
> minimum of $50.00. Still that seems good, no that seems great!
>
> Cy

min order 50$ no setup fee for 4 layer?
and free shipping?

this is pretty good if so

Antti

On Sep 22, 10:19=A0pm, nobody <cydrollin...@gmail.com> wrote:
> Looking for interest in an Open Source Hardware USB programmable FPGA,
> XC3S250E. I have been having some difficulty getting the right people
> exposed to this project. If you have any interest in this project
> would like to hear from you. It is headed into an Open Source Hardware
> agreement therefore their is no proprietary information about the
> design.
>
> Here is an image of the board.http://www.mediafire.com/imageview.php?quic=
kkey=3Dyhjjddznzmx&thumb=3D5
>
> Cy Drollinger
> Electronic Realization L.L.C.
> 313 W. Mendenhall #5
> Bozeman, MT 59715
> PH: 406-586-5502
> Email: c...@montana.net

Cy
does your company have a permananet web url?
or the product actually, i am writing september brain adding
the photo of you gadet too (with commentary)
would be nice to add link too - i will defenetly NOT link to mediafire
or something similar

Antti

Antti,

Well, Thank You. It is unexpected such help but needed. The web sight
is elec-real.com, but only a generic business page from Network
Solutions is available. I am working on getting someone or myself to
get something put together.

cy

On Sep 24, 7:30=A0am, nobody <cydrollin...@gmail.com> wrote:
> Rick,
>
> You were right, I can not refute you at this time it is $6.10 per
> board so it stands no one can do it for $6 a board. Yes, they do a
> minimum of $50.00. Still that seems good, no that seems great!
>
> Cy

Care to share who these people are? I've never seen 4-layer pricing
this low, for such small quantities.

Cy, while your broad-brush concept is commendable, the execution
leaves a little to be desired. The Arduino is successful because it's
a 80MB download with a free software toolchain, with a great deal of
abstraction that removes the need to go through the uC setting
registers. If the Arduino had been just a hardware design, it would
not have been successful. For your board one needs to download
Xilinx's immense webpack and learn the vagaries of HDL. And you're
relying on Xilinx's software for synthesis and so on, so while the
hardware design may be open, the software toolchain sure ain't. That
makes it a good deal less "Free".

- Mike

On Sep 24, 10:30=A0am, nobody <cydrollin...@gmail.com> wrote:
> Rick,
>
> You were right, I can not refute you at this time it is $6.10 per
> board so it stands no one can do it for $6 a board. Yes, they do a
> minimum of $50.00. Still that seems good, no that seems great!
>
> Cy

But I am afraid that your math is very poor.  If they have a minimum
order amount of $50, then the price is $50 per board for qty 1.  Qty 2
is $25 per board and so on until you reach the floor price of $6.10 at
qty 9.  However, if they are anything like other PCB houses, the price
will continue to drop as the volume goes up and may well drop below
$6.10 per board, I can't say for sure though.  In reality, I would bet
the $6.10 figure is for qty 100 or something similar.  It is just too
much labor to set up a PCB run to do *any* number of boards for $50,
but they may be combining your boards with some others to achieve a
lower unit cost.

Rick

On Sep 23, 12:57=A0pm, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 23, 7:38=A0pm, rickman <gnu...@gmail.com> wrote:
>
>
>
> > On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > Antti,
>
> > > I enjoy your responses they are to the bone, but valid. The right
> > > people are engineers who wish to pick this project up for their
> > > benefit, yes antti as well as mine. The engineer would be some one
> > > willing to pay a bit extra for one of four boards available with all
> > > the design file associated with the boards. These files are the meat
> > > of the work and would allow an engineer to make changes from the
> > > current form to one more suitable to their needs, if necessary. Open
> > > Source license also allows anyone willing to manufacture this product
> > > for sale and profit of their own, royalty free. Development and
> > > testing is a huge cost and has been paid for in this project. Yes,
> > > antti schematics are available for many of the development boards but
> > > firmware and how things are implemented are not. Digilent for example
> > > produced a project that only required a usb to miniB connection to th=
e
> > > board to program utilizing Xilinx's impact program, how did they do
> > > that? They will not tell me, I understand, but it was worth asking.
>
> > Yes, there are vendors who do not make all of their design files
> > available for FPGA development boards. =A0But for the most part, the
> > FPGA makers provide development boards and make all of their design
> > files available. =A0I think they do this to reduce the amount of suppor=
t
> > required. =A0If you have all of the design files, you don't need to ask
> > so many questions, you can just look it up yourself. =A0So in that
> > sense, there are a number of open source FPGA development boards.
> > Just not with the freedom to make your own copies although I can't
> > imagine an FPGA vendor would object since you would be putting their
> > parts on it!
>
> > > If the 4 layer printed circuit board was manufactured for $6 is that
> > > to expensive?
>
> > No one can have a board manufactured for $6. =A0You might be able to ge=
t
> > 100 for $600 or possibly even 10 for $60, but not 1 for $6. =A0That is
> > one of the problems with open source hardware. =A0It is "hard" and ofte=
n
> > difficult to make on your own. =A0But that does not need to be a
> > problem. =A0The most successful open source hardware (OSH) project I
> > have seen is the Beagle Board which can only be made in pretty
> > advanced factories. =A0It uses a Package on Package mounting technique
> > for the processor memory as the OMAP CPU used is intended for use in
> > PDAs and cell phone like applications. =A0So clearly, the fact that you
> > might have to sell some part or even all of the board would not doom
> > the project as Antti might think. =A0(Not trying to put words in your
> > mouth Antti, just making a point).
>
> > In fact, I am thinking about an open source GPS receiver project which
> > would require not only the electronic hardware, but also a mechanical
> > design be done. =A0Now *that* can be a problem for open source I
> > think.
>
> > > My point: is placing all of this projects work in an open source
> > > license to be easily duplicated at a reasonable cost one board under
> > > $50.00 for someone in need of well behaved electronic signals, maybe
> > > an engineer, a student, a hobbyist, and the like. Antti, you are so
> > > preceptive, Yes, I would like to be able to accept notes of
> > > appreciation for this body of work, because someone finds it helpful.
> > > Being able to discuss this body of work and let it go out to those wh=
o
> > > would find it useful makes me smile. Open Source Hardware licensing
> > > just prevents anyone from strangling the work and making it theirs,
> > > plagiarism. This body of work is not quite original but is not a rip
> > > off, or a copy of another work. Yes, their are similar projects out
> > > there and I have asked for help on this project from those similar
> > > project, but understandably I got go away, I did.
> > > I have spent my resource on this project and I need more to continue
> > > on or even try something different.
>
> > Have you defined your goals for this project? =A0If you are going to
> > succeed, you need to know what you are trying to do, *clearly*.
> > Others can give feedback on the goals and you can modify them to
> > include as many others as possible. =A0Then you will get as much suppor=
t
> > as possible.
>
> > Rick
>
> Rick,
>
> beagle is:
> 1) backed up by TI
> 2) uses (used) newest components
>
> Cy's design:
> 1) uses OBSOLETED and NFND components
>
> see the difference?
>
> Cy: doing something different is an option
>
> And as before i am failing to see what you expect to find?
>
> I can only sayd that no "open source" developer will be
> ordering and assembling those boards for personal use
> and no company is interested to produce them either
>
> so if somebody makes the boards its only you, and then
> you have boards with 2 generation too old FPGA that
> nobody is interested in, and that you can not sell even
> for break even
>
> Antti

I'm not sure what your point is.  I am sure there are any number of
differences between nobody's project and the beagleboard.  So?

Why do you think the XC3S250E is an obsolete chip?  Heck, every chip
will be off the cutting edge in six months.  Personally, I prefer to
use parts that are not brand new designs, especially with Xilinx.
They have a reputation for making their products widely available only
a long time after initial shipments to favored customers.  Do you have
any of the new parts?

As to the beagleboard being "backed up" by TI, that really doesn't
make much of a difference.  I have not seen any indication that the
people making them are financially supported by TI.  The fact that the
board can only be made by rather advanced technology assemblers means
you pretty much *have* to buy these boards rather than making your
own.  I will say that at $150 there is not much incentive to build
your own, even if you want 100's.  A much smaller board that I am
building and selling in qty 100's, with cheaper parts costs me $100 to
build.  I expect the beagleboard costs close to the selling price, so
maybe TI *is* supporting the project in some way.

My only problem with the beagleboard is that the power consumption is
too high, and that it has no FPGA ;^)  I would like something along
these lines with an ARM9 processor and memory capable of running
Linux, all designed for lowest power so it can run from batteries.
Like a PDA I guess, but more than 6 hours of run time, more like 20
hours with a PDA sized display.

I wish this was not the FPGA forum.  I don't feel I should carry on
with this discussion here.  There are some display technologies I
would like to discuss.  Maybe I'll go over to c.a.e and post there...

Rick

"Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com> wrote:

>On Sep 23, 10:47=A0pm, "Antti.Luk...@googlemail.com"
><antti.luk...@googlemail.com> wrote:
>> On Sep 23, 10:41=A0pm, nobody <cydrollin...@gmail.com> wrote:
>>
>>
>>
>> > Antti,
>>
>> > You have it all figured dont ya, Nobody, nothing, no company, no
>> > interest. Well, seems as if two others have joined in to express some
>> > interest.
>>
>> > =A0I agree the mating components, 4 connectors, used on the board for
>> > stacking the boards are expensive and therefore need to rethink
>> Antti
>> PS I am not as negative just trying to help you,
>> and yes i have pretty much figured out
>
>i must correct myself
>
>s3e: no failsafe multiboot in SPI flash without external circuitry

Whats the problem with that? The only limitation of this board is that
you need an external JTAG interface to program it. It would be nicer
to have JTAG thru the FTDI chip. That way you'll always have a
fallback.


-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

On Sep 26, 8:39=A0pm, rickman <gnu...@gmail.com> wrote:
> On Sep 23, 12:57=A0pm, "Antti.Luk...@googlemail.com"
>
>
>
> <antti.luk...@googlemail.com> wrote:
> > On Sep 23, 7:38=A0pm, rickman <gnu...@gmail.com> wrote:
>
> > > On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > > Antti,
>
> > > > I enjoy your responses they are to the bone, but valid. The right
> > > > people are engineers who wish to pick this project up for their
> > > > benefit, yes antti as well as mine. The engineer would be some one
> > > > willing to pay a bit extra for one of four boards available with al=
l
> > > > the design file associated with the boards. These files are the mea=
t
> > > > of the work and would allow an engineer to make changes from the
> > > > current form to one more suitable to their needs, if necessary. Ope=
n
> > > > Source license also allows anyone willing to manufacture this produ=
ct
> > > > for sale and profit of their own, royalty free. Development and
> > > > testing is a huge cost and has been paid for in this project. Yes,
> > > > antti schematics are available for many of the development boards b=
ut
> > > > firmware and how things are implemented are not. Digilent for examp=
le
> > > > produced a project that only required a usb to miniB connection to =
the
> > > > board to program utilizing Xilinx's impact program, how did they do
> > > > that? They will not tell me, I understand, but it was worth asking.
>
> > > Yes, there are vendors who do not make all of their design files
> > > available for FPGA development boards. =A0But for the most part, the
> > > FPGA makers provide development boards and make all of their design
> > > files available. =A0I think they do this to reduce the amount of supp=
ort
> > > required. =A0If you have all of the design files, you don't need to a=
sk
> > > so many questions, you can just look it up yourself. =A0So in that
> > > sense, there are a number of open source FPGA development boards.
> > > Just not with the freedom to make your own copies although I can't
> > > imagine an FPGA vendor would object since you would be putting their
> > > parts on it!
>
> > > > If the 4 layer printed circuit board was manufactured for $6 is tha=
t
> > > > to expensive?
>
> > > No one can have a board manufactured for $6. =A0You might be able to =
get
> > > 100 for $600 or possibly even 10 for $60, but not 1 for $6. =A0That i=
s
> > > one of the problems with open source hardware. =A0It is "hard" and of=
ten
> > > difficult to make on your own. =A0But that does not need to be a
> > > problem. =A0The most successful open source hardware (OSH) project I
> > > have seen is the Beagle Board which can only be made in pretty
> > > advanced factories. =A0It uses a Package on Package mounting techniqu=
e
> > > for the processor memory as the OMAP CPU used is intended for use in
> > > PDAs and cell phone like applications. =A0So clearly, the fact that y=
ou
> > > might have to sell some part or even all of the board would not doom
> > > the project as Antti might think. =A0(Not trying to put words in your
> > > mouth Antti, just making a point).
>
> > > In fact, I am thinking about an open source GPS receiver project whic=
h
> > > would require not only the electronic hardware, but also a mechanical
> > > design be done. =A0Now *that* can be a problem for open source I
> > > think.
>
> > > > My point: is placing all of this projects work in an open source
> > > > license to be easily duplicated at a reasonable cost one board unde=
r
> > > > $50.00 for someone in need of well behaved electronic signals, mayb=
e
> > > > an engineer, a student, a hobbyist, and the like. Antti, you are so
> > > > preceptive, Yes, I would like to be able to accept notes of
> > > > appreciation for this body of work, because someone finds it helpfu=
l.
> > > > Being able to discuss this body of work and let it go out to those =
who
> > > > would find it useful makes me smile. Open Source Hardware licensing
> > > > just prevents anyone from strangling the work and making it theirs,
> > > > plagiarism. This body of work is not quite original but is not a ri=
p
> > > > off, or a copy of another work. Yes, their are similar projects out
> > > > there and I have asked for help on this project from those similar
> > > > project, but understandably I got go away, I did.
> > > > I have spent my resource on this project and I need more to continu=
e
> > > > on or even try something different.
>
> > > Have you defined your goals for this project? =A0If you are going to
> > > succeed, you need to know what you are trying to do, *clearly*.
> > > Others can give feedback on the goals and you can modify them to
> > > include as many others as possible. =A0Then you will get as much supp=
ort
> > > as possible.
>
> > > Rick
>
> > Rick,
>
> > beagle is:
> > 1) backed up by TI
> > 2) uses (used) newest components
>
> > Cy's design:
> > 1) uses OBSOLETED and NFND components
>
> > see the difference?
>
> > Cy: doing something different is an option
>
> > And as before i am failing to see what you expect to find?
>
> > I can only sayd that no "open source" developer will be
> > ordering and assembling those boards for personal use
> > and no company is interested to produce them either
>
> > so if somebody makes the boards its only you, and then
> > you have boards with 2 generation too old FPGA that
> > nobody is interested in, and that you can not sell even
> > for break even
>
> > Antti
>
> I'm not sure what your point is. =A0I am sure there are any number of
> differences between nobody's project and the beagleboard. =A0So?
>
> Why do you think the XC3S250E is an obsolete chip? =A0Heck, every chip
> will be off the cutting edge in six months. =A0Personally, I prefer to
> use parts that are not brand new designs, especially with Xilinx.
> They have a reputation for making their products widely available only
> a long time after initial shipments to favored customers. =A0Do you have
> any of the new parts?
>
> As to the beagleboard being "backed up" by TI, that really doesn't
> make much of a difference. =A0I have not seen any indication that the
> people making them are financially supported by TI. =A0The fact that the
> board can only be made by rather advanced technology assemblers means
> you pretty much *have* to buy these boards rather than making your
> own. =A0I will say that at $150 there is not much incentive to build
> your own, even if you want 100's. =A0A much smaller board that I am
> building and selling in qty 100's, with cheaper parts costs me $100 to
> build. =A0I expect the beagleboard costs close to the selling price, so
> maybe TI *is* supporting the project in some way.
>
> My only problem with the beagleboard is that the power consumption is
> too high, and that it has no FPGA ;^) =A0I would like something along
> these lines with an ARM9 processor and memory capable of running
> Linux, all designed for lowest power so it can run from batteries.
> Like a PDA I guess, but more than 6 hours of run time, more like 20
> hours with a PDA sized display.
>
> I wish this was not the FPGA forum. =A0I don't feel I should carry on
> with this discussion here. =A0There are some display technologies I
> would like to discuss. =A0Maybe I'll go over to c.a.e and post there...
>
> Rick

Rick,
when did you last look for information for S3E based boards made by
Xilinx at Xilinx website?
if you have done it recently, go and do some search. This should
answer the issue why
S3e should not be used any more. It's not that bad chip, but S3A is
available at digikey
already for some time now, so there is no reason not to use S3A
S3A
S3AN
S3ADSP
S6
are all newer than S3E, and i have strong belive that Xilinx really
wants everyone
to use S3A and newer chips for any new designs. Correct me if i am
wrong
about this. I also feel there is no reason to use something as old as
S3E for
new designs (unless there are special reasons todo so)

Cy's designs uses

1 FT245
2 CPLD
3 S3E
4 Oscillator
5 spi flash

need 4 layer PCB and requires external JTAG to bootstrap

Anttis design would use
1 FT232R (also used for CLOCK!)
2 S3E or S3A
3 spi flash

and would bootstrap with empty components, and could
be done with 2 layer PCB

see the difference?
if you make a design for open source it doesnt mean
you should not make it as good as you can,
this is what i think, and what i have tried to say as well.

Antti

On Sep 27, 6:55=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
> "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote:
> >On Sep 23, 10:47=3DA0pm, "Antti.Luk...@googlemail.com"
> ><antti.luk...@googlemail.com> wrote:
> >> On Sep 23, 10:41=3DA0pm, nobody <cydrollin...@gmail.com> wrote:
>
> >> > Antti,
>
> >> > You have it all figured dont ya, Nobody, nothing, no company, no
> >> > interest. Well, seems as if two others have joined in to express som=
e
> >> > interest.
>
> >> > =3DA0I agree the mating components, 4 connectors, used on the board =
for
> >> > stacking the boards are expensive and therefore need to rethink
> >> Antti
> >> PS I am not as negative just trying to help you,
> >> and yes i have pretty much figured out
>
> >i must correct myself
>
> >s3e: no failsafe multiboot in SPI flash without external circuitry
>
> Whats the problem with that? The only limitation of this board is that
> you need an external JTAG interface to program it. It would be nicer
> to have JTAG thru the FTDI chip. That way you'll always have a
> fallback.
>
> --
> Failure does not prove something is impossible, failure simply
> indicates you are not using the right tools...
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg=
er hammer!"
> --------------------------------------------------------------

missing multiboot was one major issue with S3E in my opinion
other FPGA had multiboot already, Xilinx was just leaping behind
they fixed it in S3A and V5 only

multiboot is a VERY important feature, no wonder pretty much all
FPGA vendors support it in their latest families.

Ah, when we talk about open-source user programmable
USB FPGA things, I already have one on my desk, well it
isnt opened yet to public, but it soon will be, it does
use FT245 and FPGA with multiboot feature, first image
is programmed with FTDI communication and some
default FPGA applicatation that is responsible for
SPI flash update, and user application auto start,
leaving 3 FPGA configurations for the user

Antti

"Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com> wrote:

>On Sep 26, 8:39=A0pm, rickman <gnu...@gmail.com> wrote:
>> On Sep 23, 12:57=A0pm, "Antti.Luk...@googlemail.com"
>>
>>
>>
>> <antti.luk...@googlemail.com> wrote:
>> > On Sep 23, 7:38=A0pm, rickman <gnu...@gmail.com> wrote:
>>
>> > > On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>>
>> > > > Antti,
>>
>> > > > I enjoy your responses they are to the bone, but valid. The right
>> > > > people are engineers who wish to pick this project up for their
>> > > > benefit, yes antti as well as mine. The engineer would be some one
>> > > files available. =A0I think they do this to reduce the amount of supp=
>ort
>> > > required. =A0If you have all of the design files, you don't need to a=
>sk
>e
>> > > > on or even try something different.
>>
>> > > Have you defined your goals for this project? =A0If you are going to
>> > > succeed, you need to know what you are trying to do, *clearly*.
>> > > Others can give feedback on the goals and you can modify them to
>> > > include as many others as possible. =A0Then you will get as much supp=
>ort
>> > > as possible.
>>
>> > > Rick
>>
>> Linux, all designed for lowest power so it can run from batteries.
>> with this discussion here. =A0There are some display technologies I
>> would like to discuss. =A0Maybe I'll go over to c.a.e and post there...
>>
>> Rick
>
>Rick,
>when did you last look for information for S3E based boards made by
>Xilinx at Xilinx website?
>if you have done it recently, go and do some search. This should
>answer the issue why
>S3e should not be used any more. It's not that bad chip, but S3A is
>available at digikey
>already for some time now, so there is no reason not to use S3A
>S3A
>S3AN
>S3ADSP
>S6
>are all newer than S3E, and i have strong belive that Xilinx really
>wants everyone

Sorry, but this sounds like a load of crap to me. The S3E is a
perfectly useful chip. Although the pin configuration is more limited
that the standard S3 parts. You seem obsessed with flash. FYI none of
the designs I ever worked on used flash to store the FPGA
configuration. Flash isn't a big deal for everyone.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

Nico Coesel <nico@puntnl.niks> wrote:
> "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com> wrote:

> Sorry, but this sounds like a load of crap to me. The S3E is a
> perfectly useful chip. Although the pin configuration is more limited
> that the standard S3 parts. You seem obsessed with flash. FYI none of
> the designs I ever worked on used flash to store the FPGA
> configuration. Flash isn't a big deal for everyone.

But the 2.5 Volt-only JTAG is a PITA...
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

On Sep 28, 4:42=A0am, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> >
> Anttis design would use
> 1 FT232R (also used for CLOCK!)

Why not FT2232H here, to "make it as good as you can," ?

> 2 S3E or S3A
> 3 spi flash

I assume this includes SPI Flash with 2b/4b modes, again "make it as
good as you can," ? ( or maybe even 2 SPI flash devices...)

-jg

-jg <jim.granville@gmail.com> wrote:
> On Sep 28, 4:42�am, "Antti.Luk...@googlemail.com"
> <antti.luk...@googlemail.com> >
> > Anttis design would use
> > 1 FT232R (also used for CLOCK!)

> Why not FT2232H here, to "make it as good as you can," ?

The FT2232H costs more buck and needs more infrastructure. But I perfer it
too... 
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

On Sep 28, 9:48=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:
> -jg <jim.granvi...@gmail.com> wrote:
> > Why not FT2232H here, to "make it as good as you can," ?
>
> The FT2232H costs more buck and needs more infrastructure. But I perfer i=
t
> too...

  I like the potential for a reasonable rate continual sample, for
things like PC Frequency counter, Logic analyzer ets, as it's always
good to have a 'free instrument'  or two, in any development kit, and
especially so for teaching.
 { We've been getting quite good results from SoundCards, on the 'free
instrument' front, (but with obvious bandwidth ceilings) }

-jg

On Sep 27, 12:42=A0pm, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 26, 8:39=A0pm, rickman <gnu...@gmail.com> wrote:
>
>
>
> > On Sep 23, 12:57=A0pm, "Antti.Luk...@googlemail.com"
>
> > <antti.luk...@googlemail.com> wrote:
> > > On Sep 23, 7:38=A0pm, rickman <gnu...@gmail.com> wrote:
>
> > > > On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > > > Antti,
>
> > > > > I enjoy your responses they are to the bone, but valid. The right
> > > > > people are engineers who wish to pick this project up for their
> > > > > benefit, yes antti as well as mine. The engineer would be some on=
e
> > > > > willing to pay a bit extra for one of four boards available with =
all
> > > > > the design file associated with the boards. These files are the m=
eat
> > > > > of the work and would allow an engineer to make changes from the
> > > > > current form to one more suitable to their needs, if necessary. O=
pen
> > > > > Source license also allows anyone willing to manufacture this pro=
duct
> > > > > for sale and profit of their own, royalty free. Development and
> > > > > testing is a huge cost and has been paid for in this project. Yes=
,
> > > > > antti schematics are available for many of the development boards=
 but
> > > > > firmware and how things are implemented are not. Digilent for exa=
mple
> > > > > produced a project that only required a usb to miniB connection t=
o the
> > > > > board to program utilizing Xilinx's impact program, how did they =
do
> > > > > that? They will not tell me, I understand, but it was worth askin=
g.
>
> > > > Yes, there are vendors who do not make all of their design files
> > > > available for FPGA development boards. =A0But for the most part, th=
e
> > > > FPGA makers provide development boards and make all of their design
> > > > files available. =A0I think they do this to reduce the amount of su=
pport
> > > > required. =A0If you have all of the design files, you don't need to=
 ask
> > > > so many questions, you can just look it up yourself. =A0So in that
> > > > sense, there are a number of open source FPGA development boards.
> > > > Just not with the freedom to make your own copies although I can't
> > > > imagine an FPGA vendor would object since you would be putting thei=
r
> > > > parts on it!
>
> > > > > If the 4 layer printed circuit board was manufactured for $6 is t=
hat
> > > > > to expensive?
>
> > > > No one can have a board manufactured for $6. =A0You might be able t=
o get
> > > > 100 for $600 or possibly even 10 for $60, but not 1 for $6. =A0That=
 is
> > > > one of the problems with open source hardware. =A0It is "hard" and =
often
> > > > difficult to make on your own. =A0But that does not need to be a
> > > > problem. =A0The most successful open source hardware (OSH) project =
I
> > > > have seen is the Beagle Board which can only be made in pretty
> > > > advanced factories. =A0It uses a Package on Package mounting techni=
que
> > > > for the processor memory as the OMAP CPU used is intended for use i=
n
> > > > PDAs and cell phone like applications. =A0So clearly, the fact that=
 you
> > > > might have to sell some part or even all of the board would not doo=
m
> > > > the project as Antti might think. =A0(Not trying to put words in yo=
ur
> > > > mouth Antti, just making a point).
>
> > > > In fact, I am thinking about an open source GPS receiver project wh=
ich
> > > > would require not only the electronic hardware, but also a mechanic=
al
> > > > design be done. =A0Now *that* can be a problem for open source I
> > > > think.
>
> > > > > My point: is placing all of this projects work in an open source
> > > > > license to be easily duplicated at a reasonable cost one board un=
der
> > > > > $50.00 for someone in need of well behaved electronic signals, ma=
ybe
> > > > > an engineer, a student, a hobbyist, and the like. Antti, you are =
so
> > > > > preceptive, Yes, I would like to be able to accept notes of
> > > > > appreciation for this body of work, because someone finds it help=
ful.
> > > > > Being able to discuss this body of work and let it go out to thos=
e who
> > > > > would find it useful makes me smile. Open Source Hardware licensi=
ng
> > > > > just prevents anyone from strangling the work and making it their=
s,
> > > > > plagiarism. This body of work is not quite original but is not a =
rip
> > > > > off, or a copy of another work. Yes, their are similar projects o=
ut
> > > > > there and I have asked for help on this project from those simila=
r
> > > > > project, but understandably I got go away, I did.
> > > > > I have spent my resource on this project and I need more to conti=
nue
> > > > > on or even try something different.
>
> > > > Have you defined your goals for this project? =A0If you are going t=
o
> > > > succeed, you need to know what you are trying to do, *clearly*.
> > > > Others can give feedback on the goals and you can modify them to
> > > > include as many others as possible. =A0Then you will get as much su=
pport
> > > > as possible.
>
> > > > Rick
>
> > > Rick,
>
> > > beagle is:
> > > 1) backed up by TI
> > > 2) uses (used) newest components
>
> > > Cy's design:
> > > 1) uses OBSOLETED and NFND components
>
> > > see the difference?
>
> > > Cy: doing something different is an option
>
> > > And as before i am failing to see what you expect to find?
>
> > > I can only sayd that no "open source" developer will be
> > > ordering and assembling those boards for personal use
> > > and no company is interested to produce them either
>
> > > so if somebody makes the boards its only you, and then
> > > you have boards with 2 generation too old FPGA that
> > > nobody is interested in, and that you can not sell even
> > > for break even
>
> > > Antti
>
> > I'm not sure what your point is. =A0I am sure there are any number of
> > differences between nobody's project and the beagleboard. =A0So?
>
> > Why do you think the XC3S250E is an obsolete chip? =A0Heck, every chip
> > will be off the cutting edge in six months. =A0Personally, I prefer to
> > use parts that are not brand new designs, especially with Xilinx.
> > They have a reputation for making their products widely available only
> > a long time after initial shipments to favored customers. =A0Do you hav=
e
> > any of the new parts?
>
> > As to the beagleboard being "backed up" by TI, that really doesn't
> > make much of a difference. =A0I have not seen any indication that the
> > people making them are financially supported by TI. =A0The fact that th=
e
> > board can only be made by rather advanced technology assemblers means
> > you pretty much *have* to buy these boards rather than making your
> > own. =A0I will say that at $150 there is not much incentive to build
> > your own, even if you want 100's. =A0A much smaller board that I am
> > building and selling in qty 100's, with cheaper parts costs me $100 to
> > build. =A0I expect the beagleboard costs close to the selling price, so
> > maybe TI *is* supporting the project in some way.
>
> > My only problem with the beagleboard is that the power consumption is
> > too high, and that it has no FPGA ;^) =A0I would like something along
> > these lines with an ARM9 processor and memory capable of running
> > Linux, all designed for lowest power so it can run from batteries.
> > Like a PDA I guess, but more than 6 hours of run time, more like 20
> > hours with a PDA sized display.
>
> > I wish this was not the FPGA forum. =A0I don't feel I should carry on
> > with this discussion here. =A0There are some display technologies I
> > would like to discuss. =A0Maybe I'll go over to c.a.e and post there...
>
> > Rick
>
> Rick,
> when did you last look for information for S3E based boards made by
> Xilinx at Xilinx website?
> if you have done it recently, go and do some search. This should
> answer the issue why
> S3e should not be used any more. It's not that bad chip, but S3A is
> available at digikey
> already for some time now, so there is no reason not to use S3A
> S3A
> S3AN
> S3ADSP
> S6
> are all newer than S3E, and i have strong belive that Xilinx really
> wants everyone
> to use S3A and newer chips for any new designs. Correct me if i am
> wrong
> about this. I also feel there is no reason to use something as old as
> S3E for
> new designs (unless there are special reasons todo so)
>
> Cy's designs uses
>
> 1 FT245
> 2 CPLD
> 3 S3E
> 4 Oscillator
> 5 spi flash
>
> need 4 layer PCB and requires external JTAG to bootstrap
>
> Anttis design would use
> 1 FT232R (also used for CLOCK!)
> 2 S3E or S3A
> 3 spi flash
>
> and would bootstrap with empty components, and could
> be done with 2 layer PCB

Why a two layer board?  I would expect any decent design to use at
least four layers just so it can have a ground/power plane for noise
reduction.  Especially when you don't know what someone will be doing
with it, best is to provide a bit of overkill.  I'm not interested in
saving every last penny on a development board like this.

I will say that Uwe has a point about the 2.5 volt configuration
signals of the S3.  When the S3 came out they had a number of issues
with the I/Os and only a few of them were fixed in the S3.  The rest
were fixed in the S3E and S3A.

But there are often reasons for using older tech chips.  My last
design used a Lattice XP instead of the XP2 because the XP2 is not
available in the 100 pin TQFP package.  It costs more to use a higher
pin count package and is harder to layout a BGA or CS package as well
as requiring more layers and higher cost board.  In another design I
did some years back, I had to use an old tech chip to get 5 volt
tolerance.  I had to hunt around quite a bit to find an eval board for
it too!

I do agree that your ideas are better, I just don't think it is a
pointless board that no one else would be interested in.  I'm not
saying that it is anything great, but I don't think it is complete
crap either.


Rick

On Sep 27, 11:51=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
> "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote:
> >On Sep 26, 8:39=3DA0pm, rickman <gnu...@gmail.com> wrote:
> >> On Sep 23, 12:57=3DA0pm, "Antti.Luk...@googlemail.com"
>
> >> <antti.luk...@googlemail.com> wrote:
> >> > On Sep 23, 7:38=3DA0pm, rickman <gnu...@gmail.com> wrote:
>
> >> > > On Sep 23, 11:58=3DA0am, nobody <cydrollin...@gmail.com> wrote:
>
> >> > > > Antti,
>
> >> > > > I enjoy your responses they are to the bone, but valid. The righ=
t
> >> > > > people are engineers who wish to pick this project up for their
> >> > > > benefit, yes antti as well as mine. The engineer would be some o=
ne
> >> > > files available. =3DA0I think they do this to reduce the amount of=
 supp=3D
> >ort
> >> > > required. =3DA0If you have all of the design files, you don't need=
 to a=3D
> >sk
> >e
> >> > > > on or even try something different.
>
> >> > > Have you defined your goals for this project? =3DA0If you are goin=
g to
> >> > > succeed, you need to know what you are trying to do, *clearly*.
> >> > > Others can give feedback on the goals and you can modify them to
> >> > > include as many others as possible. =3DA0Then you will get as much=
 supp=3D
> >ort
> >> > > as possible.
>
> >> > > Rick
>
> >> Linux, all designed for lowest power so it can run from batteries.
> >> with this discussion here. =3DA0There are some display technologies I
> >> would like to discuss. =3DA0Maybe I'll go over to c.a.e and post there=
....
>
> >> Rick
>
> >Rick,
> >when did you last look for information for S3E based boards made by
> >Xilinx at Xilinx website?
> >if you have done it recently, go and do some search. This should
> >answer the issue why
> >S3e should not be used any more. It's not that bad chip, but S3A is
> >available at digikey
> >already for some time now, so there is no reason not to use S3A
> >S3A
> >S3AN
> >S3ADSP
> >S6
> >are all newer than S3E, and i have strong belive that Xilinx really
> >wants everyone
>
> Sorry, but this sounds like a load of crap to me. The S3E is a
> perfectly useful chip. Although the pin configuration is more limited
> that the standard S3 parts. You seem obsessed with flash. FYI none of
> the designs I ever worked on used flash to store the FPGA
> configuration. Flash isn't a big deal for everyone.
>
> --
> Failure does not prove something is impossible, failure simply
> indicates you are not using the right tools...
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg=
er hammer!"
> --------------------------------------------------------------

I very seldom call others people comments "load of crap"
sure S3e is useful chip, and i have said there could
be valid reasons to use it also (if you did read my postings)
as of S3AN <> S3A, it doesnt have to be S3AN, S3A
is pretty much useable too (or S3ADSP even better),
so if you Nico do not like Flash you could use S3A right?

"none of the designs you worked did ever use flash to store
FPGA configuration" - Nico is it really so? You never
used a desgin with Parallel Flash conf?
never a design with Serial flash conf?
xilinx platform flash is flash too, ever used?

did you only use OTP in ALL your designs?

maybe..

Antti

On Sep 28, 12:48=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:
> -jg <jim.granvi...@gmail.com> wrote:
> > On Sep 28, 4:42=A0am, "Antti.Luk...@googlemail.com"
> > <antti.luk...@googlemail.com> >
> > > Anttis design would use
> > > 1 FT232R (also used for CLOCK!)
> > Why not FT2232H here, to "make it as good as you can," ?
>
> The FT2232H costs more buck and needs more infrastructure. But I perfer i=
t
> too...
> --
> Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar=
mstadt.de
>
> Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Right Uwe,

it does cost a lot of more infrastructure, and is more expensive as
chip as well,
so thats the reason, for lowest cost it would be FT232R, for
perfromance
it would be FT2232H or CY7C68013

Antti

On Sep 28, 3:39=A0am, rickman <gnu...@gmail.com> wrote:
> On Sep 27, 12:42=A0pm, "Antti.Luk...@googlemail.com"
>
>
>
> <antti.luk...@googlemail.com> wrote:
> > On Sep 26, 8:39=A0pm, rickman <gnu...@gmail.com> wrote:
>
> > > On Sep 23, 12:57=A0pm, "Antti.Luk...@googlemail.com"
>
> > > <antti.luk...@googlemail.com> wrote:
> > > > On Sep 23, 7:38=A0pm, rickman <gnu...@gmail.com> wrote:
>
> > > > > On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > > > > Antti,
>
> > > > > > I enjoy your responses they are to the bone, but valid. The rig=
ht
> > > > > > people are engineers who wish to pick this project up for their
> > > > > > benefit, yes antti as well as mine. The engineer would be some =
one
> > > > > > willing to pay a bit extra for one of four boards available wit=
h all
> > > > > > the design file associated with the boards. These files are the=
 meat
> > > > > > of the work and would allow an engineer to make changes from th=
e
> > > > > > current form to one more suitable to their needs, if necessary.=
 Open
> > > > > > Source license also allows anyone willing to manufacture this p=
roduct
> > > > > > for sale and profit of their own, royalty free. Development and
> > > > > > testing is a huge cost and has been paid for in this project. Y=
es,
> > > > > > antti schematics are available for many of the development boar=
ds but
> > > > > > firmware and how things are implemented are not. Digilent for e=
xample
> > > > > > produced a project that only required a usb to miniB connection=
 to the
> > > > > > board to program utilizing Xilinx's impact program, how did the=
y do
> > > > > > that? They will not tell me, I understand, but it was worth ask=
ing.
>
> > > > > Yes, there are vendors who do not make all of their design files
> > > > > available for FPGA development boards. =A0But for the most part, =
the
> > > > > FPGA makers provide development boards and make all of their desi=
gn
> > > > > files available. =A0I think they do this to reduce the amount of =
support
> > > > > required. =A0If you have all of the design files, you don't need =
to ask
> > > > > so many questions, you can just look it up yourself. =A0So in tha=
t
> > > > > sense, there are a number of open source FPGA development boards.
> > > > > Just not with the freedom to make your own copies although I can'=
t
> > > > > imagine an FPGA vendor would object since you would be putting th=
eir
> > > > > parts on it!
>
> > > > > > If the 4 layer printed circuit board was manufactured for $6 is=
 that
> > > > > > to expensive?
>
> > > > > No one can have a board manufactured for $6. =A0You might be able=
 to get
> > > > > 100 for $600 or possibly even 10 for $60, but not 1 for $6. =A0Th=
at is
> > > > > one of the problems with open source hardware. =A0It is "hard" an=
d often
> > > > > difficult to make on your own. =A0But that does not need to be a
> > > > > problem. =A0The most successful open source hardware (OSH) projec=
t I
> > > > > have seen is the Beagle Board which can only be made in pretty
> > > > > advanced factories. =A0It uses a Package on Package mounting tech=
nique
> > > > > for the processor memory as the OMAP CPU used is intended for use=
 in
> > > > > PDAs and cell phone like applications. =A0So clearly, the fact th=
at you
> > > > > might have to sell some part or even all of the board would not d=
oom
> > > > > the project as Antti might think. =A0(Not trying to put words in =
your
> > > > > mouth Antti, just making a point).
>
> > > > > In fact, I am thinking about an open source GPS receiver project =
which
> > > > > would require not only the electronic hardware, but also a mechan=
ical
> > > > > design be done. =A0Now *that* can be a problem for open source I
> > > > > think.
>
> > > > > > My point: is placing all of this projects work in an open sourc=
e
> > > > > > license to be easily duplicated at a reasonable cost one board =
under
> > > > > > $50.00 for someone in need of well behaved electronic signals, =
maybe
> > > > > > an engineer, a student, a hobbyist, and the like. Antti, you ar=
e so
> > > > > > preceptive, Yes, I would like to be able to accept notes of
> > > > > > appreciation for this body of work, because someone finds it he=
lpful.
> > > > > > Being able to discuss this body of work and let it go out to th=
ose who
> > > > > > would find it useful makes me smile. Open Source Hardware licen=
sing
> > > > > > just prevents anyone from strangling the work and making it the=
irs,
> > > > > > plagiarism. This body of work is not quite original but is not =
a rip
> > > > > > off, or a copy of another work. Yes, their are similar projects=
 out
> > > > > > there and I have asked for help on this project from those simi=
lar
> > > > > > project, but understandably I got go away, I did.
> > > > > > I have spent my resource on this project and I need more to con=
tinue
> > > > > > on or even try something different.
>
> > > > > Have you defined your goals for this project? =A0If you are going=
 to
> > > > > succeed, you need to know what you are trying to do, *clearly*.
> > > > > Others can give feedback on the goals and you can modify them to
> > > > > include as many others as possible. =A0Then you will get as much =
support
> > > > > as possible.
>
> > > > > Rick
>
> > > > Rick,
>
> > > > beagle is:
> > > > 1) backed up by TI
> > > > 2) uses (used) newest components
>
> > > > Cy's design:
> > > > 1) uses OBSOLETED and NFND components
>
> > > > see the difference?
>
> > > > Cy: doing something different is an option
>
> > > > And as before i am failing to see what you expect to find?
>
> > > > I can only sayd that no "open source" developer will be
> > > > ordering and assembling those boards for personal use
> > > > and no company is interested to produce them either
>
> > > > so if somebody makes the boards its only you, and then
> > > > you have boards with 2 generation too old FPGA that
> > > > nobody is interested in, and that you can not sell even
> > > > for break even
>
> > > > Antti
>
> > > I'm not sure what your point is. =A0I am sure there are any number of
> > > differences between nobody's project and the beagleboard. =A0So?
>
> > > Why do you think the XC3S250E is an obsolete chip? =A0Heck, every chi=
p
> > > will be off the cutting edge in six months. =A0Personally, I prefer t=
o
> > > use parts that are not brand new designs, especially with Xilinx.
> > > They have a reputation for making their products widely available onl=
y
> > > a long time after initial shipments to favored customers. =A0Do you h=
ave
> > > any of the new parts?
>
> > > As to the beagleboard being "backed up" by TI, that really doesn't
> > > make much of a difference. =A0I have not seen any indication that the
> > > people making them are financially supported by TI. =A0The fact that =
the
> > > board can only be made by rather advanced technology assemblers means
> > > you pretty much *have* to buy these boards rather than making your
> > > own. =A0I will say that at $150 there is not much incentive to build
> > > your own, even if you want 100's. =A0A much smaller board that I am
> > > building and selling in qty 100's, with cheaper parts costs me $100 t=
o
> > > build. =A0I expect the beagleboard costs close to the selling price, =
so
> > > maybe TI *is* supporting the project in some way.
>
> > > My only problem with the beagleboard is that the power consumption is
> > > too high, and that it has no FPGA ;^) =A0I would like something along
> > > these lines with an ARM9 processor and memory capable of running
> > > Linux, all designed for lowest power so it can run from batteries.
> > > Like a PDA I guess, but more than 6 hours of run time, more like 20
> > > hours with a PDA sized display.
>
> > > I wish this was not the FPGA forum. =A0I don't feel I should carry on
> > > with this discussion here. =A0There are some display technologies I
> > > would like to discuss. =A0Maybe I'll go over to c.a.e and post there.=
...
>
> > > Rick
>
> > Rick,
> > when did you last look for information for S3E based boards made by
> > Xilinx at Xilinx website?
> > if you have done it recently, go and do some search. This should
> > answer the issue why
> > S3e should not be used any more. It's not that bad chip, but S3A is
> > available at digikey
> > already for some time now, so there is no reason not to use S3A
> > S3A
> > S3AN
> > S3ADSP
> > S6
> > are all newer than S3E, and i have strong belive that Xilinx really
> > wants everyone
> > to use S3A and newer chips for any new designs. Correct me if i am
> > wrong
> > about this. I also feel there is no reason to use something as old as
> > S3E for
> > new designs (unless there are special reasons todo so)
>
> > Cy's designs uses
>
> > 1 FT245
> > 2 CPLD
> > 3 S3E
> > 4 Oscillator
> > 5 spi flash
>
> > need 4 layer PCB and requires external JTAG to bootstrap
>
> > Anttis design would use
> > 1 FT232R (also used for CLOCK!)
> > 2 S3E or S3A
> > 3 spi flash
>
> > and would bootstrap with empty components, and could
> > be done with 2 layer PCB
>
> Why a two layer board? =A0I would expect any decent design to use at
> least four layers just so it can have a ground/power plane for noise
> reduction. =A0Especially when you don't know what someone will be doing
> with it, best is to provide a bit of overkill. =A0I'm not interested in
> saving every last penny on a development board like this.
>
> I will say that Uwe has a point about the 2.5 volt configuration
> signals of the S3. =A0When the S3 came out they had a number of issues
> with the I/Os and only a few of them were fixed in the S3. =A0The rest
> were fixed in the S3E and S3A.
>
> But there are often reasons for using older tech chips. =A0My last
> design used a Lattice XP instead of the XP2 because the XP2 is not
> available in the 100 pin TQFP package. =A0It costs more to use a higher
> pin count package and is harder to layout a BGA or CS package as well
> as requiring more layers and higher cost board. =A0In another design I
> did some years back, I had to use an old tech chip to get 5 volt
> tolerance. =A0I had to hunt around quite a bit to find an eval board for
> it too!
>
> I do agree that your ideas are better, I just don't think it is a
> pointless board that no one else would be interested in. =A0I'm not
> saying that it is anything great, but I don't think it is complete
> crap either.
>
> Rick

Rick

I did not say its "complete crap" as you say
look here, an USB-FPGA design with 100% open design
schematic based on S3E
http://www.oho-elektronik.de/index.php?c=3D1&s=3Dindex

as with Cy's its not perfect (the TUSB3410 is NFND)
but i do not call it crap
the GODIL can be used as USB connected FPGA
gadgets without any need for USB drivers mess, it
can be easily achived by using source code
and DLL/drivers from the code archive from
Elektor (12/2004 file name 040334-11.zip)
provided are sources for Delphi demo, tested
to work, i implemented USB EEPROM programmer
by adding only 5 lines of code
also useable with VB, provided is Word example for that

as of XP vs XP2, yeah i have some XP2 samples, but
have used XP so far, the selection of packages is
important

Antti

On Sep 28, 1:52=A0am, -jg <jim.granvi...@gmail.com> wrote:
> On Sep 28, 9:48=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
>
> darmstadt.de> wrote:
> > -jg <jim.granvi...@gmail.com> wrote:
> > > Why not FT2232H here, to "make it as good as you can," ?
>
> > The FT2232H costs more buck and needs more infrastructure. But I perfer=
 it
> > too...
>
> =A0 I like the potential for a reasonable rate continual sample, for
> things like PC Frequency counter, Logic analyzer ets, as it's always
> good to have a 'free instrument' =A0or two, in any development kit, and
> especially so for teaching.
> =A0{ We've been getting quite good results from SoundCards, on the 'free
> instrument' front, (but with obvious bandwidth ceilings) }
>
> -jg

Jim,

for those who are looking for dirt cheap usb locic and protocol
analyzer FX2 chips provide a easy solution

i first found this in some german forums, but later trapped onto this
http://www.6-lab.com/index.php/projectlist/logicu

logic-U-Plus is GENERIC FX2 board that can be configured
to emulate either Locic from
www.saleae.com
or
USBee AX Pro from
www.usbee.com

well, I have relation to those folks, and not promoting
any such use, but well, such "solutions" are available
and far more easy to use then making own logic
analyzer based on FT2232H

Antti

On Sep 28, 9:28=A0am, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 28, 1:52=A0am, -jg <jim.granvi...@gmail.com> wrote:
>
>
>
> > On Sep 28, 9:48=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
>
> > darmstadt.de> wrote:
> > > -jg <jim.granvi...@gmail.com> wrote:
> > > > Why not FT2232H here, to "make it as good as you can," ?
>
> > > The FT2232H costs more buck and needs more infrastructure. But I perf=
er it
> > > too...
>
> > =A0 I like the potential for a reasonable rate continual sample, for
> > things like PC Frequency counter, Logic analyzer ets, as it's always
> > good to have a 'free instrument' =A0or two, in any development kit, and
> > especially so for teaching.
> > =A0{ We've been getting quite good results from SoundCards, on the 'fre=
e
> > instrument' front, (but with obvious bandwidth ceilings) }
>
> > -jg
>
> Jim,
>
> for those who are looking for dirt cheap usb locic and protocol
> analyzer FX2 chips provide a easy solution
>
> i first found this in some german forums, but later trapped onto thishttp=
://www.6-lab.com/index.php/projectlist/logicu
>
> logic-U-Plus is GENERIC FX2 board that can be configured
> to emulate either Locic fromwww.saleae.com
> or
> USBee AX Pro fromwww.usbee.com
>
> well, I have relation to those folks, and not promoting
> any such use, but well, such "solutions" are available
> and far more easy to use then making own logic
> analyzer based on FT2232H
>
> Antti

OOOOOOOOOOOOOPS

CORRECTION: I have NO relation to any of those folks,
monday morning, before cofee ;)

the software from saleae/usbee is licensed for free use
only with the hardware purchased from the official
resellers, any other use is not allowed.

I'd better take a break before posting any more

Antti
PS there is place for anything and everyone
if i say something could be done better, it
doesnt mean things done otherwise are
bad to the bones, or that i could them better
myself, anything that is done, completed
and useable is something good already
no matter the techncal solutions are

On Sep 28, 6:28=A0pm, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 28, 1:52=A0am, -jg <jim.granvi...@gmail.com> wrote:
>
> > On Sep 28, 9:48=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
>
> > darmstadt.de> wrote:
> > > -jg <jim.granvi...@gmail.com> wrote:
> > > > Why not FT2232H here, to "make it as good as you can," ?
>
> > > The FT2232H costs more buck and needs more infrastructure. But I perf=
er it
> > > too...
>
> > =A0 I like the potential for a reasonable rate continual sample, for
> > things like PC Frequency counter, Logic analyzer ets, as it's always
> > good to have a 'free instrument' =A0or two, in any development kit, and
> > especially so for teaching.
> > =A0{ We've been getting quite good results from SoundCards, on the 'fre=
e
> > instrument' front, (but with obvious bandwidth ceilings) }
>
> > -jg
>
> Jim,
>
> for those who are looking for dirt cheap usb locic and protocol
> analyzer FX2 chips provide a easy solution
>
> i first found this in some german forums, but later trapped onto thishttp=
://www.6-lab.com/index.php/projectlist/logicu
>
> logic-U-Plus is GENERIC FX2 board that can be configured
> to emulate either Locic fromwww.saleae.com
> or
> USBee AX Pro fromwww.usbee.com

Those are not cheap, nor are they chips - and cannot pgm the FPGA
out of the box... - as this thread is about FPGA boards, my comments
were in that context.

ie what can do the PGM pathway _and_ give other runtime information,
almost for free.
In such single unit products, the incremental chip price variation is
not
material.
 - Digikey shows the saving to be a princely $1 ;)

 So, give the user a choice of much faster download times, and the
potential? for a free Logic/Frequency HW pathway, all for $1 more,
and
what would they choose ?

rickman <gnuarm@gmail.com> wrote:
> On Sep 27, 12:42�pm, "Antti.Luk...@googlemail.com"
> <antti.luk...@googlemail.com> wrote:
> > On Sep 26, 8:39�pm, rickman <gnu...@gmail.com> wrote:

> > > > > > I enjoy your responses they are to the bone, but valid. The right

<zillions of line of senseless quote delete>

Do people ever use archived news and get angry about unrelated quote meaning
unrelated search hits?

> Why a two layer board?  I would expect any decent design to use at
> least four layers just so it can have a ground/power plane for noise
> reduction.  Especially when you don't know what someone will be doing
> with it, best is to provide a bit of overkill.  I'm not interested in
> saving every last penny on a development board like this.

With programmable pin helping the layouter to get a planar layout, the
bottom layer can be made quite a continous groundplane.

...

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

> Do people ever use archived news and get angry about unrelated quote mean=
ing
> unrelated search hits?
>
> > Why a two layer board? =A0I would expect any decent design to use at
> > least four layers just so it can have a ground/power plane for noise
> > reduction. =A0Especially when you don't know what someone will be doing
> > with it, best is to provide a bit of overkill. =A0I'm not interested in
> > saving every last penny on a development board like this.
>
> With programmable pin helping the layouter to get a planar layout, the
> bottom layer can be made quite a continous groundplane.
>
> ..
>
> Bye
> --
> Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar=
mstadt.de
>
> Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

please complain to the GOOGLE (and saying that use something
else isnt an option always, sorry... I use what is the easiest way)
when replying using google news its not easy to delete the rubish
as it not even seen on screen

well, i see the thread is reached status where people start to
complain
about quoting issues, :(

Antti

> > logic-U-Plus is GENERIC FX2 board that can be configured
> > to emulate either Locic fromwww.saleae.com
> > or
> > USBee AX Pro fromwww.usbee.com
>
> Those are not cheap, nor are they chips - and cannot pgm the FPGA
> out of the box... - as this thread is about FPGA boards, my comments
> were in that context.
>
> ie what can do the PGM pathway _and_ give other runtime information,
> almost for free.
> In such single unit products, the incremental chip price variation is
> not
> material.
> =A0- Digikey shows the saving to be a princely $1 ;)
>
> =A0So, give the user a choice of much faster download times, and the
> potential? for a free Logic/Frequency HW pathway, all for $1 more,
> and
> what would they choose ?

Jim,

1) FT2232H prices have gone down a great deal, I wasnt even aware

well, if Cy would

1)  remove the CPLD from the design

this would be GOOD

2) replace FT245 with FT2232H

this would be GOOD also

but [2] is optional :)

Antti

On Sep 28, 12:16=A0am, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 27, 11:51=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
>
>
>
> > "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote:
> > >On Sep 26, 8:39=3DA0pm, rickman <gnu...@gmail.com> wrote:
> > >> On Sep 23, 12:57=3DA0pm, "Antti.Luk...@googlemail.com"
>
> > >> <antti.luk...@googlemail.com> wrote:
> > >> > On Sep 23, 7:38=3DA0pm, rickman <gnu...@gmail.com> wrote:
>
> > >> > > On Sep 23, 11:58=3DA0am, nobody <cydrollin...@gmail.com> wrote:
>
> > >> > > > Antti,
>
> > >> > > > I enjoy your responses they are to the bone, but valid. The ri=
ght
> > >> > > > people are engineers who wish to pick this project up for thei=
r
> > >> > > > benefit, yes antti as well as mine. The engineer would be some=
 one
> > >> > > files available. =3DA0I think they do this to reduce the amount =
of supp=3D
> > >ort
> > >> > > required. =3DA0If you have all of the design files, you don't ne=
ed to a=3D
> > >sk
> > >e
> > >> > > > on or even try something different.
>
> > >> > > Have you defined your goals for this project? =3DA0If you are go=
ing to
> > >> > > succeed, you need to know what you are trying to do, *clearly*.
> > >> > > Others can give feedback on the goals and you can modify them to
> > >> > > include as many others as possible. =3DA0Then you will get as mu=
ch supp=3D
> > >ort
> > >> > > as possible.
>
> > >> > > Rick
>
> > >> Linux, all designed for lowest power so it can run from batteries.
> > >> with this discussion here. =3DA0There are some display technologies =
I
> > >> would like to discuss. =3DA0Maybe I'll go over to c.a.e and post the=
re...
>
> > >> Rick
>
> > >Rick,
> > >when did you last look for information for S3E based boards made by
> > >Xilinx at Xilinx website?
> > >if you have done it recently, go and do some search. This should
> > >answer the issue why
> > >S3e should not be used any more. It's not that bad chip, but S3A is
> > >available at digikey
> > >already for some time now, so there is no reason not to use S3A
> > >S3A
> > >S3AN
> > >S3ADSP
> > >S6
> > >are all newer than S3E, and i have strong belive that Xilinx really
> > >wants everyone
>
> > Sorry, but this sounds like a load of crap to me. The S3E is a
> > perfectly useful chip. Although the pin configuration is more limited
> > that the standard S3 parts. You seem obsessed with flash. FYI none of
> > the designs I ever worked on used flash to store the FPGA
> > configuration. Flash isn't a big deal for everyone.
>
> > --
> > Failure does not prove something is impossible, failure simply
> > indicates you are not using the right tools...
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bi=
gger hammer!"
> > --------------------------------------------------------------
>
> I very seldom call others people comments "load of crap"
> sure S3e is useful chip, and i have said there could
> be valid reasons to use it also (if you did read my postings)
> as of S3AN <> S3A, it doesnt have to be S3AN, S3A
> is pretty much useable too (or S3ADSP even better),
> so if you Nico do not like Flash you could use S3A right?
>
> "none of the designs you worked did ever use flash to store
> FPGA configuration" - Nico is it really so? You never
> used a desgin with Parallel Flash conf?
> never a design with Serial flash conf?
> xilinx platform flash is flash too, ever used?
>
> did you only use OTP in ALL your designs?

I think the point is that it is often that the design does not use the
FPGA standalone.  It is very common that the FPGA is programmed by an
MCU or other process and does not require any separate memory of any
kind for the FPGA.

I find that most of my FPGA designs are just that way, but it is not
uncommon for my work to need dedicated memory for configuring the FPGA
as well.  I think in larger systems this is often not the case
however.

Rick

On Sep 28, 7:58=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:
> rickman <gnu...@gmail.com> wrote:
> > On Sep 27, 12:42=A0pm, "Antti.Luk...@googlemail.com"
> > <antti.luk...@googlemail.com> wrote:
> > > On Sep 26, 8:39=A0pm, rickman <gnu...@gmail.com> wrote:
> > > > > > > I enjoy your responses they are to the bone, but valid. The r=
ight
>
> <zillions of line of senseless quote delete>
>
> Do people ever use archived news and get angry about unrelated quote mean=
ing
> unrelated search hits?
>
> > Why a two layer board? =A0I would expect any decent design to use at
> > least four layers just so it can have a ground/power plane for noise
> > reduction. =A0Especially when you don't know what someone will be doing
> > with it, best is to provide a bit of overkill. =A0I'm not interested in
> > saving every last penny on a development board like this.
>
> With programmable pin helping the layouter to get a planar layout, the
> bottom layer can be made quite a continous groundplane.

Yes, that is true, but not my point.  A single ground plane does
nothing to reduce noise on the power rails.  The capacitor that is
formed by parallel planes spaced 10 mil in a PWB is the best power
supply decoupling device you can provide.  Even on a very small board,
these planes provide significant noise elimination, both in terms of
minimizing the effect on the chips and also in terms of reducing
EMI.

I realize that many designs just don't have a need for this, but my
point was that a general purpose development/eval board needs to
consider a wide range of designs including ones that push the speed of
the device and have a number of outputs switching at high edge rates.
Capacitors alone will not normally address the problem adequately in
these cases.

Rick

On Sep 28, 8:23=A0am, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> > Do people ever use archived news and get angry about unrelated quote me=
aning
> > unrelated search hits?
>
> > > Why a two layer board? =A0I would expect any decent design to use at
> > > least four layers just so it can have a ground/power plane for noise
> > > reduction. =A0Especially when you don't know what someone will be doi=
ng
> > > with it, best is to provide a bit of overkill. =A0I'm not interested =
in
> > > saving every last penny on a development board like this.
>
> > With programmable pin helping the layouter to get a planar layout, the
> > bottom layer can be made quite a continous groundplane.
>
> > ..
>
> > Bye
> > --
> > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-d=
armstadt.de
>
> > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt
> > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>
> please complain to the GOOGLE (and saying that use something
> else isnt an option always, sorry... I use what is the easiest way)
> when replying using google news its not easy to delete the rubish
> as it not even seen on screen
>
> well, i see the thread is reached status where people start to
> complain
> about quoting issues, :(

If you are using Google Groups, I hope you are clicking the spam and
reporting it.  Google seems to continue to make this easier.  The last
time I noticed, you had to open the "opions" and click "report the
message", then type at least "spam" into the edit box.  Now I see that
there is a link at the bottom of the post where you can just click
once.  It even confirms that the report has been accepted!

How much easier can it get?

Rick

On Sep 27, 2:39=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:
> Nico Coesel <n...@puntnl.niks> wrote:
> > "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote:
> > Sorry, but this sounds like a load of crap to me. The S3E is a
> > perfectly useful chip. Although the pin configuration is more limited
> > that the standard S3 parts. You seem obsessed with flash. FYI none of
> > the designs I ever worked on used flash to store the FPGA
> > configuration. Flash isn't a big deal for everyone.
>
> But the 2.5 Volt-only JTAG is a PITA...

Bingo!

Another thing is that S3E appears to be available in more packages
than S3A so you might be able to find a better fit for a particular
design.

-a

On Sep 28, 6:45=A0pm, rickman <gnu...@gmail.com> wrote:
> On Sep 28, 8:23=A0am, "Antti.Luk...@googlemail.com"
>
>
>
> <antti.luk...@googlemail.com> wrote:
> > > Do people ever use archived news and get angry about unrelated quote =
meaning
> > > unrelated search hits?
>
> > > > Why a two layer board? =A0I would expect any decent design to use a=
t
> > > > least four layers just so it can have a ground/power plane for nois=
e
> > > > reduction. =A0Especially when you don't know what someone will be d=
oing
> > > > with it, best is to provide a bit of overkill. =A0I'm not intereste=
d in
> > > > saving every last penny on a development board like this.
>
> > > With programmable pin helping the layouter to get a planar layout, th=
e
> > > bottom layer can be made quite a continous groundplane.
>
> > > ..
>
> > > Bye
> > > --
> > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu=
-darmstadt.de
>
> > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt
> > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
>
> > please complain to the GOOGLE (and saying that use something
> > else isnt an option always, sorry... I use what is the easiest way)
> > when replying using google news its not easy to delete the rubish
> > as it not even seen on screen
>
> > well, i see the thread is reached status where people start to
> > complain
> > about quoting issues, :(
>
> If you are using Google Groups, I hope you are clicking the spam and
> reporting it. =A0Google seems to continue to make this easier. =A0The las=
t
> time I noticed, you had to open the "opions" and click "report the
> message", then type at least "spam" into the edit box. =A0Now I see that
> there is a link at the bottom of the post where you can just click
> once. =A0It even confirms that the report has been accepted!
>
> How much easier can it get?
>
> Rick

I do report all spam messages, if you wanted to know that
Antti

On Sep 29, 3:40=A0am, rickman <gnu...@gmail.com> wrote:
> Yes, that is true, but not my point. =A0A single ground plane does
> nothing to reduce noise on the power rails. =A0The capacitor that is
> formed by parallel planes spaced 10 mil in a PWB is the best power
> supply decoupling device you can provide. =A0Even on a very small board,
> these planes provide significant noise elimination, both in terms of
> minimizing the effect on the chips and also in terms of reducing
> EMI.
>
> I realize that many designs just don't have a need for this, but my
> point was that a general purpose development/eval board needs to
> consider a wide range of designs including ones that push the speed of
> the device and have a number of outputs switching at high edge rates.
> Capacitors alone will not normally address the problem adequately in
> these cases.

 I'd generally agree - a demoboard such as this, should not be a
'minefield for the unwary', but the design itself should be paste-able
into someone's project.
(unless it is some highly specific FPGA subset, that only uses half a
dozen IOs, but that's a different type of demoboard... )

 A better place to drive the PCB cost down, is simply to reduce the
area.

-jg

Mike NG:

I was only vaguely aware of the adruino toolchain being open and its
ease of use, having such a large following and many are hobbyists.
Much work needs to be done on this front, but is not a show stopper. I
did a quick search for VHDL compilers and found some open license
programs, not sure how they work? OpenCores.org maybe a source for
looking into. It does seem that the ability of Xilinx toolset is
useful and not altogether useless in this particular endeavor. I like
the way it has been utilized in other projects as calls to particular
programming to put together a bin or bit or xsvf or other files of
need within a dos type command window and utilizing batch files to do
it all. I think this would be an easy transition for a Linux, or unix
user.

The board house that put these together is
overseasales@qdcircuits.net.

Nico,

I think the suggestion by you and others is valid and requires some
time and energy to make the JTAG chain within the USB communication a
reality, FT2232R.

Antti,

Still harping on the antiquated chip thing, dang. I mentioned that
this revolution of the design was for ease of build I had some S3E's
and wanted to use them in some design, I did they are consumed. The
thing about it is I can see that much of the support circuitry is up
and running putting an S6, with multiboot, in here would be possible
and would come up the first time I built it, support circuitry,
programming, power, and communication, is working. In fact trying to
get some less than 10 chips of the newly offered S6 with giga
transceivers.
I really appreciate the CPLD and will try and get it into the jtag
chain with the FT2232. I like the bus like ability of driving I/O into
or out of any pin on the FPGA, build a mux. So much of the I/O is hung
on the CPLD, this is akin to the muxes building many peripheries buses
with only the available I/O's on small MCUs. Sending out a programmed
CPLD for a project is also possible, therefore a programmable out of
the box board solution. Like the CPLD. Just add power and it is doing
the processing I have programmed in it.
Nothing is set in stone, in fact it is all ones and zeros, the ability
to change anything is possible and likely.

Uwe Bonnes,
I am not sure of the difficulty of the 2.5V vref on the jtag, but
would sure like to hear about the details. I am utilizing a ltc3455
four voltage output switching regulator which requires astonishingly
little support circuitry for a 1.2V, 1.8V, 2.5V and 3.3V at the usb
rating of ~ 2.5W.

JG

You asked the question of cheap communication for both programmming
and runtime information at an acceptable bandwidth not to mention the
power over usb. FTDI has been successful in this design and will be
looking at the FT2232 for all its communication protocols, jtag being
one of the most useful in this design. Another affordable option is
Ethernet and power over ethernet, which I have a design, but requires
about twice the funds to run prototype testing. Ethernet is a grand
solution with so much hanging on the internet, oh the possibilities.

All,

I thank you for your rich comments and ideas all have been more than
my expectations. I will be looking at many of them for another run at
at a better solution to my problem, because nothing is set in stone
and a change only requires some time, some thought, and some more of
my bad calculations. As for the discussion on the four layer board its
ability in many ways is worth the effort and cost. The complexity of
the design of the four layer board is hardly passed onto any
subsequent users, parts are still soldered onto the top or bottom not
on on the inner layers.

Antti,
you are still correct nobody still is interested in this board so I
think for now I will make it whisper BT for some marketing and fun.

Sincerely,

Cy Drollinger
Electronic Realization L.L.C.
cy@montana.net
PH: 406-586-5502
www.elec-real.com

On Sep 29, 10:35=A0am, nobody <cydrollin...@gmail.com> wrote:
> JG
>
> You asked the question of cheap communication for both programmming
> and runtime information at an acceptable bandwidth not to mention the
> power over usb. FTDI has been successful in this design and will be
> looking at the FT2232 for all its communication protocols, jtag being
> one of the most useful in this design.

Just to clarify, I was talking of their new FT2232H, which has
high speed USB.
There was a thread some weeks ago on cae, about the sustainable
data rate (no breaks/fixed tick-rate) on a 2232H, and I'm not sure
what the final answer was. 2232H has larger buffers, and higher peak
speeds, so the sustainable number has to be higher ?

-jg

On Sep 29, 1:57=A0am, -jg <jim.granvi...@gmail.com> wrote:
> On Sep 29, 10:35=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > JG
>
> > You asked the question of cheap communication for both programmming
> > and runtime information at an acceptable bandwidth not to mention the
> > power over usb. FTDI has been successful in this design and will be
> > looking at the FT2232 for all its communication protocols, jtag being
> > one of the most useful in this design.
>
> Just to clarify, I was talking of their new FT2232H, which has
> high speed USB.
> There was a thread some weeks ago on cae, about the sustainable
> data rate (no breaks/fixed tick-rate) on a 2232H, and I'm not sure
> what the final answer was. 2232H has larger buffers, and higher peak
> speeds, so the sustainable number has to be higher ?
>
> -jg

FTDI has claimed so 20MByte
this is more then 2 times less than with cypress FX2
Antti

On Sep 28, 10:00=A0am, Andy Peters <goo...@latke.net> wrote:
> Another thing is that S3E appears to be available in more packages
> than S3A so you might be able to find a better fit for a particular
> design.

That's my principle objection to the S3A family. I buy my parts from
Digi-Key, and the only non-BGA packages for S3A are the 50K devices. I
have fairly limited assembly resources so BGA / QFN parts aren't
possible, but I want larger devices. What to do?

Eric

On Sep 29, 3:05=A0am, emeb <ebromba...@gmail.com> wrote:
> On Sep 28, 10:00=A0am, Andy Peters <goo...@latke.net> wrote:
>
> > Another thing is that S3E appears to be available in more packages
> > than S3A so you might be able to find a better fit for a particular
> > design.
>
> That's my principle objection to the S3A family. I buy my parts from
> Digi-Key, and the only non-BGA packages for S3A are the 50K devices. I
> have fairly limited assembly resources so BGA / QFN parts aren't
> possible, but I want larger devices. What to do?
>
> Eric

Altera has MUCH larger selection of non-BGA packages
so you can use the latest devices and HUGE ones if you
need, all in TQFP packages

I totally agree that S3A is BAD as of package selection
but Xilinx is doing many things bad/wrong/too late

S3 - good as of LARGE parts XC3S5000 !!!
S3E - not as good any more, large parts dropped, but larger part in
nonBGA as in S3A
S3A - good configuration options (multiboot) bad package options
S3AN - even worse package options
S3ADSP - large and better than S3A, but only 2 devices
S6 - better in some terms, but again limited package options

so there is never a best, its compromise so or so

S3A has multiboot, and need one power supply less than S3E
but you are pretty much limited to S3A(N) 50 if talking non BGA
while S3E gives 500 part in TQFP100

yes, actually if thinking S3E or S3A then winner is: Cyclone III :)

Cy@ dont give up ;) there is rule of thumb: it takes 6+ month
from initial product launch til you may hope some interest (sales)
your 6 months isnt past yet

S3E multiboot can be implemented using 0.49$ MCU adding
and expensive CPLD (bad $/feature ratio) to the board give
no benefits to the user, it makes the PCB and documentation
more expensive, yes you always have to consider documentation
as cost item, you spend time (or you pay$$ for someone todo it)

Antti

On Sep 29, 11:27=A0am, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 29, 1:57=A0am, -jg <jim.granvi...@gmail.com> wrote:
>
>
>
> > On Sep 29, 10:35=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > JG
>
> > > You asked the question of cheap communication for both programmming
> > > and runtime information at an acceptable bandwidth not to mention the
> > > power over usb. FTDI has been successful in this design and will be
> > > looking at the FT2232 for all its communication protocols, jtag being
> > > one of the most useful in this design.
>
> > Just to clarify, I was talking of their new FT2232H, which has
> > high speed USB.
> > There was a thread some weeks ago on cae, about the sustainable
> > data rate (no breaks/fixed tick-rate) on a 2232H, and I'm not sure
> > what the final answer was. 2232H has larger buffers, and higher peak
> > speeds, so the sustainable number has to be higher ?
>
> > -jg
>
> FTDI has claimed so 20MByte

Has anyone confirmed this is a sustainable ('gapless') rate ?

> this is more then 2 times less than with cypress FX2

The price is also quite a bit lower for FT2232H, and it is sure to
replace a FT232R rather easier.
The speed jump from FT232R to FT2232H, is larger than the smaller
extra gain of the FX2.

20MByte (if supported thru windows) is a good logic analyser, or
Counter sampling rate.

FX2 prices seem to be climbing, and something like a UC3A3 has
a LOT more bang for less $$ (but admittedly  is newer, so has less
infrastructure right now.. )

UC3A3 really needs a lower pin count member, for this sort of
FPGA+USB_Instruments application.
-jg

> Looking for interest in an Open Source Hardware USB programmable FPGA,
> XC3S250E. I have been having some difficulty getting the right people
> exposed to this project. If you have any interest in this project
> would like to hear from you. It is headed into an Open Source Hardware
> agreement therefore their is no proprietary information about the
> design.

Resources available here http://www.fpgaz.com/usbp/index.html and here
http://www.myhdl.org/doku.php/users:cfelton:projects:usbp

On Sep 28, 8:05=A0pm, emeb <ebromba...@gmail.com> wrote:
> On Sep 28, 10:00=A0am, Andy Peters <goo...@latke.net> wrote:
>
> > Another thing is that S3E appears to be available in more packages
> > than S3A so you might be able to find a better fit for a particular
> > design.
>
> That's my principle objection to the S3A family. I buy my parts from
> Digi-Key, and the only non-BGA packages for S3A are the 50K devices. I
> have fairly limited assembly resources so BGA / QFN parts aren't
> possible, but I want larger devices. What to do?

This is one of my complaints about FPGA vendors.  Of course, they are
responding to the market and the profit figure.  But my designs
typically use small, cramped boards and BGAs are typically not an
improvement over the right size leaded package.  Yes, the BGA looks
smaller on the data sheet, but they typically require a board with
more layers and they use real estate on *both* sides of the board
unless you want to use some pretty exotic technology such as blind
vias.  I did a calculation yesterday and found that one of the two low
pin count leadless packages for the S6 parts uses less real estate
than a 100 TQFP by going to a 0.5 mm ball pitch.  The other one is
"smaller" but after counting the other side of the board as being
used, actually is 30% larger with a 0.8 mm ball pitch.

And that doesn't consider that these parts are all moe expensive
because of the higher I/O count making higher testing costs.

I'm just not a fan of BGA and CS technology for my designs.

Rick

On Sep 29, 9:41=A0am, rickman <gnu...@gmail.com> wrote:
> On Sep 28, 8:05=A0pm, emeb <ebromba...@gmail.com> wrote:
>
> > On Sep 28, 10:00=A0am, Andy Peters <goo...@latke.net> wrote:
>
> > > Another thing is that S3E appears to be available in more packages
> > > than S3A so you might be able to find a better fit for a particular
> > > design.
>
> > That's my principle objection to the S3A family. I buy my parts from
> > Digi-Key, and the only non-BGA packages for S3A are the 50K devices. I
> > have fairly limited assembly resources so BGA / QFN parts aren't
> > possible, but I want larger devices. What to do?
>
> This is one of my complaints about FPGA vendors. =A0Of course, they are
> responding to the market and the profit figure. =A0But my designs
> typically use small, cramped boards and BGAs are typically not an
> improvement over the right size leaded package. =A0Yes, the BGA looks
> smaller on the data sheet, but they typically require a board with
> more layers and they use real estate on *both* sides of the board
> unless you want to use some pretty exotic technology such as blind
> vias. =A0I did a calculation yesterday and found that one of the two low
> pin count leadless packages for the S6 parts uses less real estate
> than a 100 TQFP by going to a 0.5 mm ball pitch. =A0The other one is
> "smaller" but after counting the other side of the board as being
> used, actually is 30% larger with a 0.8 mm ball pitch.

I agree, I am usually looking for small footprint high logic resource
parts.  It is odd, the vendors might have missed some opportunities
here.  I come across more and more designers with these needs.  Most
designers simply opt out and force a small footprint uC to work (or
barely work).  At one point I was excited about the Actel QFNs but
they have these non-standard dual row/column QFNs.  And when I do use
a high pin-count BGA majority of the pins are unused.

"Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com> wrote:

>On Sep 27, 11:51=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
>> "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote:
>> >On Sep 26, 8:39=3DA0pm, rickman <gnu...@gmail.com> wrote:
>> >> On Sep 23, 12:57=3DA0pm, "Antti.Luk...@googlemail.com"
>>
>> >> <antti.luk...@googlemail.com> wrote:
>> >> > On Sep 23, 7:38=3DA0pm, rickman <gnu...@gmail.com> wrote:
>>
>> >> > > On Sep 23, 11:58=3DA0am, nobody <cydrollin...@gmail.com> wrote:
>>
>> >> > > > Antti,
>>
>> >> > > > I enjoy your responses they are to the bone, but valid. The righ=
>t
>> >> > > > people are engineers who wish to pick this project up for their
>> that the standard S3 parts. You seem obsessed with flash. FYI none of
>> the designs I ever worked on used flash to store the FPGA
>> configuration. Flash isn't a big deal for everyone.
>>
>> --
>> Failure does not prove something is impossible, failure simply
>> indicates you are not using the right tools...
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg=
>er hammer!"
>> --------------------------------------------------------------
>
>I very seldom call others people comments "load of crap"

Me too.

>sure S3e is useful chip, and i have said there could
>be valid reasons to use it also (if you did read my postings)
>as of S3AN <> S3A, it doesnt have to be S3AN, S3A
>is pretty much useable too (or S3ADSP even better),
>so if you Nico do not like Flash you could use S3A right?
>
>"none of the designs you worked did ever use flash to store
>FPGA configuration" - Nico is it really so? You never
>used a desgin with Parallel Flash conf?
>never a design with Serial flash conf?
>xilinx platform flash is flash too, ever used?

Never.

>did you only use OTP in ALL your designs?

Nope. In my world there is always a microcontroller or SoC which has
very convenient ways to update firmware and other data (including the
FPGA configuration). On one design I worked on there can be several
different I/O modules connected to an FPGA. The microcontroller first
loads a small default config and after that the FPHA config for the
particular module is loaded.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

On Sep 29, 7:41=A0am, rickman <gnu...@gmail.com> wrote:
> On Sep 28, 8:05=A0pm, emeb <ebromba...@gmail.com> wrote:
>
> > On Sep 28, 10:00=A0am, Andy Peters <goo...@latke.net> wrote:
>
> > > Another thing is that S3E appears to be available in more packages
> > > than S3A so you might be able to find a better fit for a particular
> > > design.
>
> > That's my principle objection to the S3A family. I buy my parts from
> > Digi-Key, and the only non-BGA packages for S3A are the 50K devices. I
> > have fairly limited assembly resources so BGA / QFN parts aren't
> > possible, but I want larger devices. What to do?
>
> This is one of my complaints about FPGA vendors. =A0Of course, they are
> responding to the market and the profit figure. =A0But my designs
> typically use small, cramped boards and BGAs are typically not an
> improvement over the right size leaded package. =A0Yes, the BGA looks
> smaller on the data sheet, but they typically require a board with
> more layers and they use real estate on *both* sides of the board
> unless you want to use some pretty exotic technology such as blind
> vias. =A0I did a calculation yesterday and found that one of the two low
> pin count leadless packages for the S6 parts uses less real estate
> than a 100 TQFP by going to a 0.5 mm ball pitch. =A0The other one is
> "smaller" but after counting the other side of the board as being
> used, actually is 30% larger with a 0.8 mm ball pitch.
>
> And that doesn't consider that these parts are all moe expensive
> because of the higher I/O count making higher testing costs.
>
> I'm just not a fan of BGA and CS technology for my designs.
>
> Rick

I'm with you on this. I'm doing hobby stuff, so I want small-ish
boards and inexpensive, readily available parts. I ended up using an
S3E250 in a VQ100 package. I use slave serial mode and load it up from
an ARM processor, with the bitfile stored in a micro SD card. Here's
more on the design:

http://members.cox.net/ebrombaugh1/synth/armfpga/index.html

It's a fun little board and it came up without any major hitches. Just
two layers too.

Eric

I like the site and the board, nice work! what is your intention for
the board looks like everything is available for another to reproduce
it. I dont get it whats the deal with only two layers, four is only
two more?

Sincerely,

Cy

On Sep 29, 10:22=A0pm, nobody <cydrollin...@gmail.com> wrote:
> I like the site and the board, nice work! what is your intention for
> the board looks like everything is available for another to reproduce
> it. I dont get it whats the deal with only two layers, four is only
> two more?
>
> Sincerely,
>
> Cy

it is a nice board!
something even i may want to have, i have one spare 100E
maybe i just order this PCB :)

what with 2 layers?

some can do on 2, some cant.
thats the difference.

sure 4 is only 2 more than 2
and 6 is only 2 more than 4
so why not start with 12 layers?


Antti

On Sep 29, 12:29=A0pm, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:
> On Sep 29, 10:22=A0pm, nobody <cydrollin...@gmail.com> wrote:
>
> > I like the site and the board, nice work! what is your intention for
> > the board looks like everything is available for another to reproduce
> > it. I dont get it whats the deal with only two layers, four is only
> > two more?
>
> > Sincerely,
>
> > Cy
>
> it is a nice board!
> something even i may want to have, i have one spare 100E
> maybe i just order this PCB :)
>
> what with 2 layers?
>
> some can do on 2, some cant.
> thats the difference.
>
> sure 4 is only 2 more than 2
> and 6 is only 2 more than 4
> so why not start with 12 layers?
>
> Antti

@Cy - Thanks for the compliments. The board fab I use charges
significantly more for 4 layers than 2, so I try to do 2 layers only.
My original intention was to make the design available for some of the
folks on a mail list devoted to using FPGAs for electronic music.
After I built & tested it no one else ever followed though.

@Antti - Thanks. All the design materials are free for any use,
although I haven't included any specific copyright claims/releases. I
should probably do that.

FWIW, you can buy the boards directly from the fab I use. Cost is
about $32.50/ea plus ~$15 setup/shipping. Lead time is about 3wks.
Here's a link to their site with the details:

http://www.batchpcb.com/product_info.php?products_id=3D19296&check=3D609ea2=
9581046016e0079ea8cd47a059

(BTW - I don't get anything out of this except a warm glow of
achievement)

Let me know if you have questions about it. Email addr is on my
webpage.

Eric

nobody <cydrollinger@gmail.com> wrote:

>I like the site and the board, nice work! what is your intention for
>the board looks like everything is available for another to reproduce
>it. I dont get it whats the deal with only two layers, four is only
>two more?

When using really cheap pcb makers like makepcb.com a 4 layer board is
twice as expensive as a 2 layer board. Besides, a 4 layer board isn't
a requirement. I recenty did an FPGA design on a 2 layer board. Used
the bottom layer as a ground plane and put 2 rings and a plane
underneath the FPGA on the top layer. And ofcourse a size 0402
decoupling capacitor on each power supply pin.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

On Sep 29, 2:00=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
> I recenty did an FPGA design on a 2 layer board. Used
> the bottom layer as a ground plane and put 2 rings and a plane
> underneath the FPGA on the top layer. And of course a size 0402
> decoupling capacitor on each power supply pin.

That's similar to what I did: on the backside I had ground plane plus
a 'snail-shell' of 3 concentric supply traces with vias through to the
top where the VQ100 package sits. I used 0603 caps on every supply pin
- some on the back, some on the front. Didn't have any supply
problems.

FWIW - I'm impressed that you used 0402 parts. I haven't tried to
handle parts that small yet, but I'm getting pretty good at the 0603s.

Eric

The idea of obsolete has come up a couple of times in this discussion
and I would like to take a minute to address it. Being a single
engineer in an office somewhere I do not have much time to redesign,
therefore one design to fit a multitude of applications. My
applications are growing with the times and speed is key, a single bit
stream ripping through copper at an increasing bandwidth, even though
a GT may be pushing several gigs it requires 10s of gigs to support
the rising edge of the digital signal. It has been said that the chip
is outdated the board design was not meant specifically for the chip
but for upcoming chips and the gigabit tranciever resources that are
coming at a decreasing price. The chip may be obsolete but my four
layer board design is not and will support a bga chip and GT
resources. There is a reason for xilinx application notes such as
xapp623 and xapp489 get it done once and be get it done right. I am
not saying that anybodies project is wrong but there is a reason for
four and more layers, it may not be for hobbyist but again I am not a
hobbyist.

respectfully

Cy Drollinger

emeb <ebrombaugh@gmail.com> wrote:

>On Sep 29, 2:00=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
>> I recenty did an FPGA design on a 2 layer board. Used
>> the bottom layer as a ground plane and put 2 rings and a plane
>> underneath the FPGA on the top layer. And of course a size 0402
>> decoupling capacitor on each power supply pin.
>
>That's similar to what I did: on the backside I had ground plane plus
>a 'snail-shell' of 3 concentric supply traces with vias through to the
>top where the VQ100 package sits. I used 0603 caps on every supply pin
>- some on the back, some on the front. Didn't have any supply
>problems.
>
>FWIW - I'm impressed that you used 0402 parts. I haven't tried to
>handle parts that small yet, but I'm getting pretty good at the 0603s.

We had the board (18" x 8") assembled. But it is possible to mount
0402 parts by hand. It just takes some getting used to like handling
0603 parts once did. You'll need a magnifier for inspection though.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

On Sep 30, 7:02=A0pm, nobody <cydrollin...@gmail.com> wrote:
> The idea of obsolete has come up a couple of times in this discussion
> and I would like to take a minute to address it. Being a single
> engineer in an office somewhere I do not have much time to redesign,
> therefore one design to fit a multitude of applications. My
> applications are growing with the times and speed is key, a single bit
> stream ripping through copper at an increasing bandwidth, even though
> a GT may be pushing several gigs it requires 10s of gigs to support
> the rising edge of the digital signal. It has been said that the chip
> is outdated the board design was not meant specifically for the chip
> but for upcoming chips and the gigabit tranciever resources that are
> coming at a decreasing price. The chip may be obsolete but my four
> layer board design is not and will support a bga chip and GT
> resources. There is a reason for xilinx application notes such as
> xapp623 and xapp489 get it done once and be get it done right. I am
> not saying that anybodies project is wrong but there is a reason for
> four and more layers, it may not be for hobbyist but again I am not a
> hobbyist.
>
> respectfully
>
> Cy Drollinger

Cy..
do whatever you like.. :) 4 layers is too little actually..
6 to 10 is more likely layer count for "real boards"

just i got the impression you hoped that lots of
hobby open-source people would build your 4-layer
board using your gerber files.

I do not think that will be case.. that the point
i was trying to make.

Antti

Antti,

You seem to need to slam my stuff as if it is incorrect, that's a
difference between you and I. My project as it stands is what it is
and suits my purpose, however others may find use of such a project
and am trying to make it available. Other boards and projects
mentioned on this forum are what they are and suit their purpose. But
when an individual makes remarks about obsolete, not useful, not
necessary and the like explanation is necessary. As engineers we are
to take the body of knowledge we have been allotted and use it, break
it, expand it and make a contribution. If younger engineers read our
comments for their enhancement they should be unbiased and factual as
possible. If one were to read over these post they might think that
there is no need for a four layer board and as you commented that is
just not true. I take offense with your comment about a "real board"
needing 6 - 10 layers, well, taken in jest, nope, not funny. Let us
try and keep our communication at as high technical level as possible.

My points about this post's origination: 1. I have completed a project
that is affordable and can be built by a hobbyist. 2. Is there any
need for an open source project with these mentioned
capabilities?

I appreciate all the comments on this post and has been very
educational.

Cy Drollinger

On Sep 30, 9:02=A0am, nobody <cydrollin...@gmail.com> wrote:

> The chip may be obsolete but my four
> layer board design is not and will support a bga chip and GT
> resources.

You do realize that most chip families are not pinout-compatible with
one another? IOW, a Spartan6 in 256BGA is not going to work on a board
designed for a Spartan3AN?

And as I tried to get you to understand on the Xilinx PicoBlaze forum
-- there's no such thing as a "standardized FPGA platform" (as much as
Xilinx would have you believe otherwise). An audio-processing design
has very little in common with a video-processing system.

You choose an FPGA and design a board to meet the product
requirements. You don't try to make your product requirements fit any
random board you might already have built.

-a

On Sep 30, 8:19=A0pm, nobody <cydrollin...@gmail.com> wrote:
> Antti,
>
> You seem to need to slam my stuff as if it is incorrect, that's a
> difference between you and I. My project as it stands is what it is
> and suits my purpose, however others may find use of such a project
> and am trying to make it available. Other boards and projects
> mentioned on this forum are what they are and suit their purpose. But
> when an individual makes remarks about obsolete, not useful, not
> necessary and the like explanation is necessary. As engineers we are
> to take the body of knowledge we have been allotted and use it, break
> it, expand it and make a contribution. If younger engineers read our
> comments for their enhancement they should be unbiased and factual as
> possible. If one were to read over these post they might think that
> there is no need for a four layer board and as you commented that is
> just not true. I take offense with your comment about a "real board"
> needing 6 - 10 layers, well, taken in jest, nope, not funny. Let us
> try and keep our communication at as high technical level as possible.
>
> My points about this post's origination: 1. I have completed a project
> that is affordable and can be built by a hobbyist. 2. Is there any
> need for an open source project with these mentioned
> capabilities?
>
> I appreciate all the comments on this post and has been very
> educational.
>
> Cy Drollinger

i did not say YOUR board is obsoleted.
but that S3E should be considered "obsolete, NFND.."
relax, you did what you needed, used IC what you had.

do it 4, do 2 or 10, its place for everything..
boards of the complexity of your board "might be done"
on two layers, not always possible, but some have
succeeded in that. It "costs" more to design a two layer
board then a 4 layer board (6 layer).

not useful? you say it? You havent published anything real,
that would make your board more useful then others,
its not the board, it the supplementary things:

documentation, software, examples, and support.
if you do those very well, you can succeed in selling your product as
well.

sorry if you feel like threated unfair with my commentary, I tried to
say
what may help you make things better, but you go saying i am too hard
in the comments, yes i am, and better so, you go stronger, and make
it better next time, where it can be done better, i hope.

sorry, if i see you put a CPLD onto low cost board without ANY
reason for it, then its wasting resources..adding cost to the end
user.
sorry i did point it out.

eh, keep on, smile.

cheer up! The S3E "Sample Pack" board that Digilent did for Xilinx,
is a REAL bad design, bad to the bones, much bad, really, and that
was done for Xilinx by their official partner.
your board is better if that makes you feel any better.


Antti
PS I just found two of those S3E sample pack boards,
probably the best thing todo with them is to trash them
giving them away is not a good idea, hm, maybe Altera
would say me a nice word if i give them away?
(because the xilinx s3e sample boards are
anti-ads for Xilinx)

PPS I had a 24 hour battle with Xilinx BMM error..
so please excuse my wording, you too Cy..

On Sep 30, 8:32=A0pm, Andy Peters <goo...@latke.net> wrote:
> On Sep 30, 9:02=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > The chip may be obsolete but my four
> > layer board design is not and will support a bga chip and GT
> > resources.
>
> You do realize that most chip families are not pinout-compatible with
> one another? IOW, a Spartan6 in 256BGA is not going to work on a board
> designed for a Spartan3AN?
>
> And as I tried to get you to understand on the Xilinx PicoBlaze forum
> -- there's no such thing as a "standardized FPGA platform" (as much as
> Xilinx would have you believe otherwise). An audio-processing design
> has very little in common with a video-processing system.
>
> You choose an FPGA and design a board to meet the product
> requirements. You don't try to make your product requirements fit any
> random board you might already have built.
>
> -a

he probably refers to those small white connectors
but what does the design has todo with MGT's is
a bit mystery to me too

Antti