hi
how can i instantiate EDN core (exported from PlanAhead) in top level
of a verilog design , while the core doesnot have any associated I/O
buffers and gives same error in ISE mapping.

mh wrote:

>hi
>how can i instantiate EDN core (exported from PlanAhead) in top level
>of a verilog design , while the core doesnot have any associated I/O
>buffers and gives same error in ISE mapping.
>
>  
>
you can create a verilog wrapper, keeping the same ports, and 
instantiate the wrapper in your top level verilog. This wrapper will be 
empty and XST will cosider it a black box, but ngdbuild should pick up 
your edif.
make sure you place the edif in the design directory.
Aurash

-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

dear Aurash
thank you for your helpful reply. It really solved my problem.

regards
MH






Aurelian Lazarut wrote:
> mh wrote:
>
> >hi
> >how can i instantiate EDN core (exported from PlanAhead) in top level
> >of a verilog design , while the core doesnot have any associated I/O
> >buffers and gives same error in ISE mapping.
> >
> >
> >
> you can create a verilog wrapper, keeping the same ports, and
> instantiate the wrapper in your top level verilog. This wrapper will be
> empty and XST will cosider it a black box, but ngdbuild should pick up
> your edif.
> make sure you place the edif in the design directory.
> Aurash
>
> --
>  __
> / /\/\ Aurelian Lazarut
> \ \  / System Verification Engineer
> / /  \ Xilinx Ireland
> \_\/\/
>  
> phone:	353 01 4032639
> fax:	353 01 4640324