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Verilog module not working,binary division,shifting problem!!

Sorry for my poor english :/
I want to divide unsigned binary integers using non-restoring division!
I have found te algorithm here:
http://stackoverflow.com/questions/12133810/non-restoring-division-algorithm

I have implemented the algorithm on verilog.But for some reason the module does not work correct! 
The module code:
I have comented where i think the mistake is!
module divider(
    output reg[7:0] q,    
    output reg[7:0] r,   
    input [7:0] a, b);
 
	 reg[7:0] A;
	 reg[7:0] B;
	 reg[7:0] Q;
	 reg[7:0] M;
	 reg[7:0] N;
	 
	
	 always @(*)
		begin			
		
		A=8'b00000000;
		Q=a;
		M=b;
		N=8;
		
		while(N > 0)begin		 
					
		  if( A < 0 )
		  begin		  
                    A=A<<1;
		    Q=Q<<1;
		    A=A+M;
		  end
		  else 
		  begin
                    //When N=8 A=00000000  
		    A=A<<1;//I have done debugging and here does not shift A with 1 bit,it must but it doesnt why??
		    Q=Q<<1;
		    A=A-M;
		  end
		  if( A < 0 )
		  begin
		    Q[0]=0;
		    N=N-1;
		  end
		  else begin
		     Q[0]=1;
	             N=N-1;
	          end
		end
		if(A<0)begin
		  A=A+M;
		end
		q=Q;
		r=A;
		 
	end

endmodule

Can anyone find where is my mistake?? Thank you!
0
11/4/2013 9:17:07 PM
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Kristo Godari wrote:
> Sorry for my poor english :/
> I want to divide unsigned binary integers using non-restoring division!
> I have found te algorithm here:
> http://stackoverflow.com/questions/12133810/non-restoring-division-algorithm
> 
> I have implemented the algorithm on verilog.But for some reason the module does not work correct! 
> The module code:
> I have comented where i think the mistake is!
> module divider(
>     output reg[7:0] q,    
>     output reg[7:0] r,   
>     input [7:0] a, b);
>  
> 	 reg[7:0] A;
> 	 reg[7:0] B;
> 	 reg[7:0] Q;
> 	 reg[7:0] M;
> 	 reg[7:0] N;
> 	 
> 	
> 	 always @(*)
> 		begin			
> 		
> 		A=8'b00000000;
> 		Q=a;
> 		M=b;
> 		N=8;
> 		
> 		while(N > 0)begin		 
> 					
> 		  if( A < 0 )
> 		  begin		  
>                     A=A<<1;
> 		    Q=Q<<1;
> 		    A=A+M;
> 		  end
> 		  else 
> 		  begin
>                     //When N=8 A=00000000  
> 		    A=A<<1;//I have done debugging and here does not shift A with 1 bit,it must but it doesnt why??
> 		    Q=Q<<1;
> 		    A=A-M;
> 		  end
> 		  if( A < 0 )
> 		  begin
> 		    Q[0]=0;
> 		    N=N-1;
> 		  end
> 		  else begin
> 		     Q[0]=1;
> 	             N=N-1;
> 	          end
> 		end
> 		if(A<0)begin
> 		  A=A+M;
> 		end
> 		q=Q;
> 		r=A;
> 		 
> 	end
> 
> endmodule
> 
> Can anyone find where is my mistake?? Thank you!

I don't really want to debug this for you, but one thing I noticed
is that you're testing for less than zero on A, which is an unsigned
8-bit reg.  If you want to test for less than zero, A should be
declared as a signed reg.  If you really wanted to test for the
MSB of A being set, then say "if (A[7])" rather than "if (A < 0)"

-- 
Gabor
0
gabor (80)
11/4/2013 9:46:47 PM
Kristo,

First of all please don't post multiple times.  (Here and comp.lang.verilog).
Stay on the same thread too.

Now, onto the code.  There's some fundamental issues.  You're idea
is fine - you're coding up basic long division like you do
with pen and paper.  Just a few tripping points.

>module divider(
>    output reg[7:0] q,    
>    output reg[7:0] r,   
>    input [7:0] a, b);
> 
>	 reg[7:0] A;
>	 reg[7:0] B;
>	 reg[7:0] Q;
>	 reg[7:0] M;
>	 reg[7:0] N;
>	 
>	
>	 always @(*)
>		begin			
>		
>		A=8'b00000000;
>		Q=a;
>		M=b;
>		N=8;
>		
>		while(N > 0)begin		 

I suggest changing this to a 'for' loop.  Most synthesizers can handle
for loops (if you follow certain rules).  While loops can cause more trouble.

>					
>		  if( A < 0 )

Verilog Reg are default unsigned - and I suggest you stick with the default for
now.

Knowing this, you'll should see holes in your code.  This if clause is always
false.  It will never execute.

>		  begin		  
>                    A=A<<1;
>		    Q=Q<<1;
>		    A=A+M;
>		  end
>		  else 
>		  begin
>                    //When N=8 A=00000000  
>		    A=A<<1;//I have done debugging and here
>		    Q=Q<<1;
>		    A=A-M;
>		  end
>		  if( A < 0 )

This clause too, will never happen.

>		  begin
>		    Q[0]=0;
>		    N=N-1;
>		  end
>		  else begin
>		     Q[0]=1;
>	             N=N-1;
>	          end
>		end
>		if(A<0)begin

This one too - never occurs.

>		  A=A+M;
>		end
>		q=Q;
>		r=A;
>		 
>	end
>
>endmodule

That's a start.  I haven't check the math, but you're moving 
in the right direction.

Regards,

Mark
0
gtwrek1 (40)
11/4/2013 9:57:26 PM
Thank you Mark  for your Help :)
I found my mistake!
I was shifting A and Q separately!
My A at the begining is 00000000 when i shift it with a bit it gave me 00000000 and i thought that shift was not working.
Instead i want to shift AQ! Let's assume A=01011 and Q=10010 
i want to shift AQ  1 bit to the left so i can have 10111 00100!

I know how to shift AQ by one bit:
 AQ={A,Q};
 AQ=AQ<<1;

but i dont know how to separate AQ in A and Q after shifting :(
Any idea how to do that?
Thanks Kristo
 

0
11/4/2013 10:34:44 PM
Kristo Godari wrote:
> Thank you Mark  for your Help :)
> I found my mistake!
> I was shifting A and Q separately!
> My A at the begining is 00000000 when i shift it with a bit it gave me 00000000 and i thought that shift was not working.
> Instead i want to shift AQ! Let's assume A=01011 and Q=10010 
> i want to shift AQ  1 bit to the left so i can have 10111 00100!
> 
> I know how to shift AQ by one bit:
>  AQ={A,Q};
>  AQ=AQ<<1;
> 
> but i dont know how to separate AQ in A and Q after shifting :(
> Any idea how to do that?
> Thanks Kristo
>  
> 
You mean like:

  {A,Q} = {A,Q} << 1;

This shifts both together as a pair.  High bit of Q shifts
into the low bit of A.  0 shifts in from the right.  High
bit of A drops off the left.

-- 
Gabor
0
gabor (80)
11/5/2013 1:43:57 PM
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