Virtex4: I don't understand their thinking....

So after looking at the Virtex4 line of devices and their associated
features
(http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
little miffed at their chip resource allocation.

First of all, suppose I'm planning on filling an FPGA full of logic. I'm
probably going to run the majority of that logic in the same clock domain so
I don't need a whole lot of DCMs. However, I do need some way to get my data
to/from the chip. What's up with zero transceivers on the "logic platform"?
The same can be asked of the "signal processing platform". I was so looking
forward to getting away from the old parallel I/O issues, and if I'm going
to have to deal with that, maybe we better leave those DCMs on there. It
wouldn't take very many transceivers to alleviate the issue.

Second, what about those of us who build and prototype digital bus
controllers, routers, and similar applications. In that situation I'm
looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs,
a fair amount of logic, and not much else. DSP and Processors don't really
help me in that type of application, yet to get what I need I will end up
spending the extra money for the FX chip.


0
Brannon
6/10/2004 6:36:38 PM
comp.arch.fpga 18522 articles. 1 followers. Post Follow

13 Replies
180 Views

Similar Articles

[PageSpeed] 28
Brannon, wait until Xilinx releases the real details, and I am sure you
will like them.
There is a lot of flexibility in the I/O on all Virtex-4 families.
As to the large number of global clock lines and DCMs, Xilinx must to
cater to a wide range of customers, and some need them. If you need
less, you can always leave them unused, but if you need more than are
available, you (and we) would have a serious problem.

DSP circuits can be used for many other functions than DSP.  :-)
Be patient...
Peter Alfke


Brannon King wrote:
> 
> So after looking at the Virtex4 line of devices and their associated
> features
> (http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
> little miffed at their chip resource allocation.
> 
> First of all, suppose I'm planning on filling an FPGA full of logic. I'm
> probably going to run the majority of that logic in the same clock domain so
> I don't need a whole lot of DCMs. However, I do need some way to get my data
> to/from the chip. What's up with zero transceivers on the "logic platform"?
> The same can be asked of the "signal processing platform". I was so looking
> forward to getting away from the old parallel I/O issues, and if I'm going
> to have to deal with that, maybe we better leave those DCMs on there. It
> wouldn't take very many transceivers to alleviate the issue.
> 
> Second, what about those of us who build and prototype digital bus
> controllers, routers, and similar applications. In that situation I'm
> looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs,
> a fair amount of logic, and not much else. DSP and Processors don't really
> help me in that type of application, yet to get what I need I will end up
> spending the extra money for the FX chip.
0
Peter
6/10/2004 4:36:31 PM
I bet the answer you get from Xilinx will be along the lines of "we analysed
X number of designs from our customer base and found these three to be the
best fit (to maximise our profits)". They won't actually say the bit in
parentheses, but that's what they're in business for. Fair enough.
I guess the 'new' architecture makes it somewhat easier to add further
variants. After all, they've only used three letters (LSF) so far, that
leaves space for 23 more mixes! ;-)
I'm excited that the block structure will finally make partial
reconfiguration a reality.
cheers, Syms.


0
Symon
6/10/2004 4:48:27 PM
Brannon,

Well, one can either say the glass is half full, or half empty.

In an extensive survey of customers, we organized the Virtex 4 family 
into the LX, FX, and SX.

The idea was pretty simple:  we have a lot of customers today who do not 
use the MGTs, and want more logic for less cost(LX).  They feel that 
they could have a lower cost solution if we did not put MGTs and 405PPCs 
in the chip (which they end up not using).

Then there are those that like the MGTs.  They have found that the MGTs 
go well with the 405PPCs, and those that like the PPCs often find use 
for the MGTs.  The logic and BRAM has to be sufficient to balance these 
applications out, so the FX family is targeted for those folks.

Then there are the DSP folks, (who quite frankly are happy with no one 
and nothing!).  They want humongous amounts of DSP specific 
functionality (logic?  who needs logic?).  The SX family is intended for 
them.  If we wished to add the MGTs to the SX family, then we have to 
ask, do they also need 405PPCs (as the two go together very well in 
talking to users).  Maybe they do?  Maybe they should?

Three major families.

If there is a significant demand for a hybrid of the feature sets, well, 
talk to us about it.  With ASMBL, it can be done without moving heaven 
and earth.  But remember that we supply a general purpose solution (now 
three general purpose solutions) so the chip has to have an almost 
universal appeal to a market segment, or it is not worth the effort to 
do it.

As for clocks, I am happy to hear you only use one clock, but consensus 
is that we need to supply more global (and local) clocks with increasing 
   numbers of CLBs to meet our customers' requirements.

Prototyping ASICs is no longer our "big" business.  In fact, it has 
gotten progressively smaller over the years as ASICs get progressively 
more difficult to do at all.  We love when people just have to have the 
largest parts we make, however.

If the mask for the next ASIC costs $2 million, then the cost (price) of 
the FX vs. the LX is not an issue anyway.

Austin

Brannon King wrote:
> So after looking at the Virtex4 line of devices and their associated
> features
> (http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
> little miffed at their chip resource allocation.
> 
> First of all, suppose I'm planning on filling an FPGA full of logic. I'm
> probably going to run the majority of that logic in the same clock domain so
> I don't need a whole lot of DCMs. However, I do need some way to get my data
> to/from the chip. What's up with zero transceivers on the "logic platform"?
> The same can be asked of the "signal processing platform". I was so looking
> forward to getting away from the old parallel I/O issues, and if I'm going
> to have to deal with that, maybe we better leave those DCMs on there. It
> wouldn't take very many transceivers to alleviate the issue.
> 
> Second, what about those of us who build and prototype digital bus
> controllers, routers, and similar applications. In that situation I'm
> looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs,
> a fair amount of logic, and not much else. DSP and Processors don't really
> help me in that type of application, yet to get what I need I will end up
> spending the extra money for the FX chip.
> 
> 
0
Austin
6/10/2004 4:52:59 PM
"Brannon King" wrote:

>So after looking at the Virtex4 line of devices and their associated
>features
>(http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
>little miffed at their chip resource allocation.

Oh, everyone is miffed at chip resource allocation.  Almost always.
But for different reasons.  Just for a second, think about this from
Xilinx's point of view:

They can't make lots of different chips.  Each different type adds to
the development costs, support costs, inventory costs and sales costs.

Some of their customers need lots of (Pick one: RAM, IOs, DCMs,
processors, transceivers, multipliers, LUTS and FFs).  Many other
customers need less or could even care less.  For example, I've never
worked on a chip that had a reasonable use for a multiplier since the
XC4000 days, when there wasn't any multipliers!

So the chips Xilinx make must be compromises.  What I see in the
Virtex4 line is the following:

1) The logic platform is reasonable for things that are basically data
movers/processors with RAM buffers.  Yes, transceivers might be useful
for some, but parallel IO isn't dead yet, and will not be dead as long
as DDR SDRAM is the commodity memory technology.  Probably not enough
internal memory, but I'm sure there are other opinions!

2) The DSP platform is probably reasonable for DSP.  Perhaps someone
more versed in the DSP would could comment?

3) The full-featured platform should cover most other uses, but expect
to pay for features you don't need.

Now, did Xilinx miss any large volume uses of FPGAs?  I don't think
so.  Sure, a prototype router might require no hard processor, no
multipliers and other DSP support, and the designer will need to buy
the FX chip with these features, but how many of these are going to be
built?

YMMV, SRA, SDD, OMNHO, ...


--
Phil Hays
Phil_hays at posting domain should work for email

0
Phil
6/10/2004 5:25:19 PM
Symon,

Ha ha ha.

That was really funny (really, it was).  Almost quoted me chapter and verse.

And I would hope it is OK with everyone that Xilinx continues to make 
money so that we can enable all of you to do likewise.

Glad you are not puzzled by any of this.

Austin

Symon wrote:
> I bet the answer you get from Xilinx will be along the lines of "we analysed
> X number of designs from our customer base and found these three to be the
> best fit (to maximise our profits)". They won't actually say the bit in
> parentheses, but that's what they're in business for. Fair enough.
> I guess the 'new' architecture makes it somewhat easier to add further
> variants. After all, they've only used three letters (LSF) so far, that
> leaves space for 23 more mixes! ;-)
> I'm excited that the block structure will finally make partial
> reconfiguration a reality.
> cheers, Syms.
> 
> 
0
Austin
6/10/2004 6:08:37 PM
Hey,

Why so much negativity on this board regarding V4 already? It's the
most kick-ass and awesome FPGA ever made. How bout some kudos and a
big thanks to Xilinx for stepping up to the plate and hitting one out
of the park?

If you think the parts are not planned right or no thinking was put
into it you are on a different planet. The people with the most desire
for the right features determined the results. I really don't think
Xilinx told their customers what they need. So I would humbly submit
to you that if you don't understand the thinking, then you don't
understand the market.

Anyway, let's get a bit excited on this board about the most
significant advancement in FPGA technology in several years. It will
completely blow Stratix II and anything else out of the water in every
regard. Great thinking and innovation seem to be poured into V4.

500 MHz all over the place.
3 versions, Everything, logic, DSP
PPC 405
600 to 11 Gbps I/O
1 Gbps I/O on every pin

Sounds pretty spectacular to me. So get a bit excited and have some
positive thinking out there. V4 SX, LX, and FX are going to be the
standard in 90 nm FPGA technology.

Yeah!


"Brannon King" <bking@starbridgesystems.com> wrote in message news:<ca9v66$m5@dispatch.concentric.net>...
> So after looking at the Virtex4 line of devices and their associated
> features
> (http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
> little miffed at their chip resource allocation.
> 
> First of all, suppose I'm planning on filling an FPGA full of logic. I'm
> probably going to run the majority of that logic in the same clock domain so
> I don't need a whole lot of DCMs. However, I do need some way to get my data
> to/from the chip. What's up with zero transceivers on the "logic platform"?
> The same can be asked of the "signal processing platform". I was so looking
> forward to getting away from the old parallel I/O issues, and if I'm going
> to have to deal with that, maybe we better leave those DCMs on there. It
> wouldn't take very many transceivers to alleviate the issue.
> 
> Second, what about those of us who build and prototype digital bus
> controllers, routers, and similar applications. In that situation I'm
> looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs,
> a fair amount of logic, and not much else. DSP and Processors don't really
> help me in that type of application, yet to get what I need I will end up
> spending the extra money for the FX chip.
0
seannstifler69
6/11/2004 6:14:07 AM
Can you point me to some technical data on the enhanced partial
reconfig capabilities?  I'm very interested in this area and I can't
seem to find anything on Xilinx's site that wasn't written by somebody
from the marketing department.

  - a

"Symon" <symon_brewer@hotmail.com> writes:
> I bet the answer you get from Xilinx will be along the lines of "we analysed
> X number of designs from our customer base and found these three to be the
> best fit (to maximise our profits)". They won't actually say the bit in
> parentheses, but that's what they're in business for. Fair enough.
> I guess the 'new' architecture makes it somewhat easier to add further
> variants. After all, they've only used three letters (LSF) so far, that
> leaves space for 23 more mixes! ;-)
> I'm excited that the block structure will finally make partial
> reconfiguration a reality.
> cheers, Syms.
>
>

-- 
"The first time I read this book I felt what I could only explain as a
 great disturbance in the Force: it was as if a billion washing
 machinces all became unbalanced at once and were suddenly silenced."

                             -- anonymous book reviewer on Amazon.com
0
Adam
6/11/2004 8:28:20 AM
"Stifler" <seannstifler69@hotmail.com> wrote in message
news:bf780a06.0406102214.3bc26509@posting.google.com...
> Hey,
>
> Why so much negativity on this board regarding V4 already? It's the
> most kick-ass and awesome FPGA ever made. How bout some kudos and a
> big thanks to Xilinx for stepping up to the plate and hitting one out
> of the park?

Has it been made yet?  I was real happy to see the announcement but a bit
disappointed that it didn't come with some data sheets for a good
architectural description with all the minutia about resources available in
the planned parts.  I'm okay with not having working silicon for a short
while but I think some of the backlash on this board was because of the
insensitive tease.  Bait the engineers with something that looks very good
but don't give them any real meat.  I'm looking forward to further news.

> If you think the parts are not planned right or no thinking was put
> into it you are on a different planet. The people with the most desire
> for the right features determined the results. I really don't think
> Xilinx told their customers what they need. So I would humbly submit
> to you that if you don't understand the thinking, then you don't
> understand the market.
>
> Anyway, let's get a bit excited on this board about the most
> significant advancement in FPGA technology in several years. It will
> completely blow Stratix II and anything else out of the water in every
> regard. Great thinking and innovation seem to be poured into V4.

You may be overstating a bit to suggest this is "the most significant
advancement" since the features are almost everything we've already seen.
The PPC, the MGT, the CLB structure (I believe) are all pretty much the
same.  The evolutionary features that are attractive include the enhanced
DSP elements including hardware divide and the no-overhead FIFO mode for the
BlockRAMs.  Neat stuff, but it doesn't come across as a revolutionary
product.  Evolutionary is fine.

Didn't Stratix-II come out with a "revolutionary" change to the LUT
structures to allow interesting input configurations such as independent
3-bit and 5-bit input functions without chewing up other resources?  A
little flexibility is a good thing.  Don't get me wrong - I like the LUTs we
get from Xilinx thanks to the memory and SRL capabilities;  I've used them
virtually unchanged for years and years.

> 500 MHz all over the place.
> 3 versions, Everything, logic, DSP
> PPC 405
> 600 to 11 Gbps I/O
> 1 Gbps I/O on every pin

A nice feature set, indeed.

> Sounds pretty spectacular to me. So get a bit excited and have some
> positive thinking out there. V4 SX, LX, and FX are going to be the
> standard in 90 nm FPGA technology.
>
> Yeah!

I'm hoping Xilinx continues to deliver the price/performance advantages
we've come to enjoy.
Looking forward to it!


0
John_H
6/11/2004 3:44:12 PM
Symon wrote:
> 
> I'm excited that the block structure will finally make partial
> reconfiguration a reality.

I missed something.  I don't see anything that talks about partial
reconfiguration and what I do see indicates these parts are still
designed around columns.  

I am still waiting for modular configuration support for Spartan 3.  I
was told over six months ago that they had just a couple of issues that
needed to be addressed before they could provide this and that Xilinx
was commited to providing this feature.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
0
rickman
6/11/2004 4:12:41 PM
Adam,
I don't know any technical details, but it struck me that the block
structure is ideally suited to partial reconfiguration on a block by block
basis. It's like lots of mini FPGAs on one die, much more than it was
before. I don't believe that Xilinx will pass up this opportunity to tune
the software to allow block by block P&R etc. I envisage an application, a
bit like Ultracontroller, that demonstrates 'partial configuration for
dummies' of a ASBL block with a standardised interface to adjacent blocks.
I'd recommend pestering your FAE, if enough people are interested or, more
importantly, enough people will use this feature, I'm sure the marketing
machine will respond! From my point of view, with an FPGA with as many gates
as these parts will have, I think partial reconfiguration will become the
norm as more and more little ASICs are converted to IP and hoovered up into
the FPGA.
cheers, Syms.

"Adam Megacz" <adam@megacz.com> wrote in message
news:m13c521ot7.fsf@nowhere.com...
>
> Can you point me to some technical data on the enhanced partial
> reconfig capabilities?  I'm very interested in this area and I can't
> seem to find anything on Xilinx's site that wasn't written by somebody
> from the marketing department.
>
>   - a


0
Symon
6/11/2004 4:17:37 PM
Rick,
I'm so excited that maybe my grammar got away from me. Try replacing
'excited' with 'optimistic' to get what I meant. The 'new' thing that Xilinx
is pushing is this ASBL block structure. Surely(!?) they've designed these
blocks to be easily individually programmable? Especially as valued
customers like us have been pushing for it for years?
Cheers, Syms.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:40C9D9F9.E6D04ADB@yahoo.com...
> Symon wrote:
> >
> > I'm excited that the block structure will finally make partial
> > reconfiguration a reality.
>
> I missed something.  I don't see anything that talks about partial
> reconfiguration and what I do see indicates these parts are still
> designed around columns.
>


0
Symon
6/11/2004 4:45:43 PM
I would be willing to bet NOT.  I don't see any sign that the ASBL
blocks relate to configuration blocks.  Yeah, it would be a great think
if they could do that, but I'm not holding my breath.  


Symon wrote:
> 
> Rick,
> I'm so excited that maybe my grammar got away from me. Try replacing
> 'excited' with 'optimistic' to get what I meant. The 'new' thing that Xilinx
> is pushing is this ASBL block structure. Surely(!?) they've designed these
> blocks to be easily individually programmable? Especially as valued
> customers like us have been pushing for it for years?
> Cheers, Syms.
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:40C9D9F9.E6D04ADB@yahoo.com...
> > Symon wrote:
> > >
> > > I'm excited that the block structure will finally make partial
> > > reconfiguration a reality.
> >
> > I missed something.  I don't see anything that talks about partial
> > reconfiguration and what I do see indicates these parts are still
> > designed around columns.
> >

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
0
rickman
6/11/2004 5:45:00 PM
The real question is not if the support partial reconfiguration ... but you
and how many others want it... there was a partially configurable Xilinx
....once .. many years ago... but it came and went.. this is capitalism not
fantasy money talks the rest walk.
So unless someone is willing to spend $$$ partial reconfiguration is an
electric dream. and if you really need it.. put down 2 devices :-)

Simon


"Symon" <symon_brewer@hotmail.com> wrote in message
news:2iu5tqFqvetqU1@uni-berlin.de...
> Rick,
> I'm so excited that maybe my grammar got away from me. Try replacing
> 'excited' with 'optimistic' to get what I meant. The 'new' thing that
Xilinx
> is pushing is this ASBL block structure. Surely(!?) they've designed these
> blocks to be easily individually programmable? Especially as valued
> customers like us have been pushing for it for years?
> Cheers, Syms.
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:40C9D9F9.E6D04ADB@yahoo.com...
> > Symon wrote:
> > >
> > > I'm excited that the block structure will finally make partial
> > > reconfiguration a reality.
> >
> > I missed something.  I don't see anything that talks about partial
> > reconfiguration and what I do see indicates these parts are still
> > designed around columns.
> >
>
>


0
Simon
6/12/2004 5:31:07 AM
Reply:
Similar Artilces:

price difference, filemaker thinks europeans are rich ! ?
I would like to know why filemaker is only 299$ in the usa ( 218 euros ) and in France it is 571$ ( 417 Euros) in europe. I am disgusted by such politics in pricing ( comparable to adobe ) that i decided to buy a competitor product instead. Pat. In article <46d9ac39$0$7769$426a74cc@news.free.fr>, "patate" <misterbanned@hotmail.com> wrote: > I would like to know why filemaker is only 299$ in the usa ( 218 euros ) > and in France it is 571$ ( 417 Euros) in europe. > > I am disgusted by such politics in pricing ( comparable to adobe ) that i > de...

Virtex4: where is ICAP?
When designing for partial reconfiguration, the ICAP port has to be into the fixed part of the design. ok, but where is it in the xc4vlx60? at the bottom of central column? It's in the center of the center column. Regards, -Trevor bob wrote: > When designing for partial reconfiguration, the ICAP port has to be into the fixed part of the design. > > ok, but where is it in the xc4vlx60? > > at the bottom of central column? ...

Thinking of implementing RAC?
If your organization is thinking about implementing RAC using 64 bit architecture, in the US, in the next 6 months, please contact me off-line. I am looking for a demonstration site for a proof of concept. The organization must have at least 3TB of data and, needless to say, there will be some very substantial financial benefits to the site chosen. Thank you. -- Daniel A. Morgan University of Washington damorgan@x.washington.edu (replace 'x' with 'u' to respond) ...

The importance of understanding cellular-automata
To validate a typology (this will be a paper for "Personality and Individua= l Differences"), I need to survey about twenty people familiar with all fou= r of the following:=20 1. Evolutionary computation 2. Supervised learning 3. Cellular-automata 4. The processes behind a standard calculator I have created an online survey at http://goo.gl/tJjQrb. It takes about 15 = minutes, and has already been completed by the most obvious experts (encour= aging results so far, but publication will require a larger sample). Thank you to anyone who can help by answering the survey...

Please help me understand my code
Hi, I know a little about Fortran. I am reading a program. I have several questions. SUBROUTINE XYZ ... DO II = FGPM(7), 1, -1 IF (TSOIL(II) .LE. 0.) GOTO 6543 ENDDO FRZD = 0. IF (fgco(1) .LT. 0.) frzd = tsoil(8) GOTO 6542 6543 IF (II .EQ. 1) THEN DZ1 = - 0.5*FGPM(8) ELSE DZ1 = 0.5*(FGPM(7+II-1)-FGPM(7+II)) ENDIF IF (TSOIL(II) .EQ. 0.) THEN FRZD = - (DZ1+FGPM(7+II))*100. ELSE DZ2 = FGP...

I completely understand why my iMac hasn't been delivered yet...
.... it's so blatantly obvious I'm not the least bit upset with Apple... On 31 Jul 2006 17:18:09 -0700, "Edwin" <thorne25@juno.com> wrote: > >... it's so blatantly obvious I'm not the least bit upset with Apple... No doubt its for the same reason I haven't gotten my fully loaded MacBook Pro yet. Mayor of R'lyeh wrote: > On 31 Jul 2006 17:18:09 -0700, "Edwin" <thorne25@juno.com> wrote: > > > > >... it's so blatantly obvious I'm not the least bit upset with Apple... > > No doubt its for the ...

Chipscope and Virtex4 LX25 ES
Hi, Xilinx solution 20060 refers to the issue with the Virtex 4 LX25 ES parts and the JTAG chains, with workarounds for the EDK's XMD and opb_mdm tools. However, this silicon bug also affects ChipScope Pro, but no solution is offered. We are considering prototyping a large project on the ML401 (which uses V4-LX25 ES parts), but ChipScope support will be essential. Does anybody have some good news for me that there is, or soon will be, a workaround for this? Thanks, John ChipScope works actually with LX25-ES but you can not use MDM and Chipscope in the same design thats the lim...

US-TX-Austin: Project Manager, Project Management, Understanding of healthcare i (45306657607)
US-TX-Austin: Project Manager, Project Management, Understanding of healthcare i (45306657607) ============================================================================================== Position: Project Manager Reference: JAH00001 Location: Austin TX Duration: 8 mont Skills: Project Management Understanding of healthcare industry Excellent at tracking details SAP OR PeopleSoft type knowledge a plus. Scope: Do not have pre-defined questions, but in general we will be looking at the specific...

???? i can`t understand it
This is a multi-part message in MIME format. ------=_NextPart_000_0006_01C35D95.66393000 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit >>> a=[1,2,3,4,5] >>> for b in a: .... a.remove(b) .... >>> a [2, 4] >>> ------=_NextPart_000_0006_01C35D95.66393000 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text...

virtex4 distributed RAM
Hi, I'm looking for Timing info on an Asynchronous FIFO built using Distributed RAM on Virtex4. the part # we are using is : LX100-10, package FF1513. Xilinx publishes the FIFO timing info for Asynchronous FIFOs using Block RAM, but not distributed RAM. Specifically, I'd like to know the timing of all the FIFO signals (FULL/EMPTY, ALMOST_FYLL/ALMOST_EMPTY and other FIFO status signals). If someone could shed some light on where I might find this info, I'd really appreciate it. Why do you want to use distributed RAM, when you can get a ready-made high-performance FIFO in each Block...

Re: Adaptive thinking #3
Mark Wonsil wrote, > > This will get the juices flowing for HP World... > > IBM overhauls iSeries for the long haul > > It's been a pattern for years in the server market: A > powerful new machine > arrives, grows popular, then fades into history as the ....snip... > > Full story: http://zdnet.com.com/2100-1103_2-5300765.html > One item from the article, left out in Mark's quote, has particular bearing on the demise of the HP 3000: "The processor switch in 1995, to IBM's Power processors--used in the company's Unix ser...

Do you think Walt Mossberg will be severely reprimanded for leaking the 3G iphone? no more pre-release apple toys for this reporter?
"there will be a 3G iphone in the next 60 days" i cannot believe he let that slip-out. probably didn't realise he was being filmed! i wonder if apple are pissed at him for breaking his NDA. he does work for a giant paper. (i think the WSJ is equivalent to the Times here) His reviews are very good and surely contribute to a lot of sales. ...

pci 6025E understanding samples to read and Rate
I have PCI-6025E Maximum 200K Samples/second, 16 analog input and 12 bit resolution. In NI DAQ Assistant, I would like to read 15 analog channels from ai0 to ai14. Acquisition mode : N samples Clock settings &nbsp;&nbsp;&nbsp;&nbsp; Samples to read:&nbsp; 10000 &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...

Help needed (understand C function)
Hi I have the code below I do not know if the code section in comments " CAN THE FOLLOWING CODE EVER BE CALLED ? " is really called Any help is appreciated. Thanks --------------------------------------------------------------------- static void E0001(int IENTRY,int *status,double *x,double *fx, double *xlo,double *xhi,unsigned long *qleft, unsigned long *qhi,double *zabstl,double *zreltl, double *zxhi,double *zxlo) { #define ftol(zx) (0.5e0*fifdmax1(abstol,reltol*fabs((zx)))) static double a,abstol,b,c,d,fa,fb,fc,fd,fda,fdb,...

Bug in Default[] or Bug in My Understanding?
In[208]:= ClearAll[f] ; Default[f,2] = 0; In[210]:= f[a_, b_.] := a + b In[211]:= f[1] Out[211]= 1 In[212]:= (* Now change Default *) Default[f,2] = 1; (* Note that Mathematica seems to recognize change *) In[213]:= ?f Global`f f[a_,b_.]:=a+b f/:Default[f,2]=1 (* But not really! Expected 2 *) In[214]:= f[1] Out[214]= 1 Even if it is a rule that you can't change the Default after the function is defined it is certainly not nice of Mathematica to allow such a change and advertise the change in the output of Definition[] and Information[]. I am using 6.0.2.0 ...

REal tough problem //// Read carefuly to understand
I have this code : start script niv=value; % just a value example niv= 20; >>>here do something<<<<<< % from here result the value of """Maxim""" Here need to compute the value of >>>>prag<<<< but I dont know if I must ADD or make minus % % Example: let's say Maxim = 25 so execute >> if (maxim<50) prag=(niv + %niv/2)+0.01; but if the result is not what i want then make minus % prag=(niv - niv/2)+0.01; ...

Trying to understand Rice's Theorem
http://www.pmfst.unist.hr/~milica/Matem_teorija_r/MTR_web/Introduction%20To%20Automata%20Theory.pdf Pages 387-390 Hofcroft says (on page 388) "We can not recognize a set of languages as the languages themselves. The reason is that the typical language, being infinite, cannot be written down as a finite-length string that could be input to a TM." Isn't the single language a*b* fully expressed by the regular expression, and isn't it a single language and not multiple languages? Even languages as complex as English would seem to be able to be fully expressed ...

just trying to understand
You can see I'm quite new to this. VB5. Trying to play a sound using embedding. So I put an OLE control in the form and created an object from file. Here's the code hoping to produce an exe for use in another pc: Private Declare Function PlaySound Lib "winmm.dll" Alias "PlaySoundA" (ByVal lpszName As String, ByVal hModule As Long, ByVal dwFlags As Long) As Long ' ............................................................ Private Sub Command1_Click() PlaySound "c:\windows\media\microsoft office 2000\gunshot.wav", 0, 0 End Sub When I run the exe ...

What's the current thinking on lengthening battery life?
(Yeah, I know that "system" is supposed to mean "operating system," but there's hardly any activities in the Mac hardware groups.) I checked the Help files on my new MacBook Air but couldn't find any guidance about whether it's okay to leave the computer plugged in all the time or whether I should let the battery run down and then recharge it. What are considered best practices for lithium-polymer batteries? Patty On 2015-06-22, Patty Winter <patty1@sonic.net> wrote: > (Yeah, I know that "system" is supposed to mean "oper...

J2EE Deploytool thinks WAR file is empty
Deploytool will not deploy my application (EAR file) because it says one of the WAR files contains no components. At the same time, Deploytool shows that the WAR file contains a JSP file. When I try to deploy the app using Ant, I get the following errors: CLI171 Command deploy failed : Fatal Error from EJB Compiler -- JDO7 4030: JDOCodeGenerator: Caught an IOException initializing CMP code generation for application 'OrderProcessingCenterEAR' module 'po-ejb': JDO7001: Cannot findresource com/sun/jdo/spi/persistence/generator/database/${DBVENDORNAME}.properties. DO7...

Virtex4 CLKX2 DCM Jitter
I guess this is really one for Austin, but I wonder if anyone else has any input. My company supplys a design which is used in a V4LX25. The design uses external QDR SRAM @ 200MHz (400MBit). The design has a built in memory test which exercises the memories under worst case conditions (flat out) with pseudo random address/data, and all works well. However, the jitter on the Kclock to the memories gets a lot higher (>600pS) when this test is running. When the system is idle the jitter is <100pS. These "jitter" measurements are simply read off the scope eye pattern which...

FIFO16 on virtex4 error?
I am currently using FIFO16 with xilinx Virtex-4. I found out in my design, the "almostempty" "almostfull" "empty" "full" flags are all stay high. That means some errors happen. The FIFO16s are configured as: width 36 depth 512 almostempty offset 12'd128 almostfull offset 12'd256 first word fall through (FWFT) Mode "True" read_clk 162Mhz write_clk 200Mhz Is there any issues here? It's been reseted before use, (reset assertion time is more than 3 clock cycles for both read and write clock). Anyone have similar experience o...

US-TX-Austin: Project Eng/Sr Analyst, Understanding of computer compnents; 9M (45348214401)
US-TX-Austin: Project Eng/Sr Analyst, Understanding of computer compnents; 9M (45348214401) =========================================================================================== Position: Project Eng/Sr Analyst Reference: SMC01986 Location: Austin TX Duration: 9M Skills: A strong understanding of the effects of each computer component (motherboards, drivers, operating systems, peripherals, etc.) is essential. The candidate should use methodical troubleshooting to solve a wide range of problems in i...

sample for virtex4
i m look for a sample for virtex4 fx12 from avnet there are 3 week, i'm trying to make a flickering led on my board, an nothing. I'm using ise 7 all sample from avnet are microblaze ou power pc May be if y found a sample in vhdl/verilog/shematic to virtex4 i understand why my design are false Thank's Fran´┐Żois Rigaud --------------= Posted using GrabIt =---------------- ------= Binary Usenet downloading made easy =--------- -= Get GrabIt for free from http://www.shemes.com/ =- ...

RESOUR> [NetGold] TELECOMMUNICATIONS: WIRELESS: Understanding and Developing Skills and Knowledge of WiFi
From: NetHappenings Moderator Date: Tue, 11 May 2004 08:43:24 -0500 To: comp.internet.net-happenings Subject: RESOUR> [NetGold] TELECOMMUNICATIONS: WIRELESS: Understanding and Developing Skills and Knowledge of WiFi ************************************************************** Educational CyberPlayGround http://www.edu-cyberpg.com/ ************************************************************** Net Happenings Mailing List Net Happenings Service <http://www.edu-cyberpg.com/Community/Subguidelines.html> Subscribe | Unsubscribe | Change Email Preferences - <http://w...