Virtex4: I don't understand their thinking....

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So after looking at the Virtex4 line of devices and their associated
features
(http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
little miffed at their chip resource allocation.

First of all, suppose I'm planning on filling an FPGA full of logic. I'm
probably going to run the majority of that logic in the same clock domain so
I don't need a whole lot of DCMs. However, I do need some way to get my data
to/from the chip. What's up with zero transceivers on the "logic platform"?
The same can be asked of the "signal processing platform". I was so looking
forward to getting away from the old parallel I/O issues, and if I'm going
to have to deal with that, maybe we better leave those DCMs on there. It
wouldn't take very many transceivers to alleviate the issue.

Second, what about those of us who build and prototype digital bus
controllers, routers, and similar applications. In that situation I'm
looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs,
a fair amount of logic, and not much else. DSP and Processors don't really
help me in that type of application, yet to get what I need I will end up
spending the extra money for the FX chip.


0
Reply Brannon 6/10/2004 6:36:38 PM

See related articles to this posting


Brannon, wait until Xilinx releases the real details, and I am sure you
will like them.
There is a lot of flexibility in the I/O on all Virtex-4 families.
As to the large number of global clock lines and DCMs, Xilinx must to
cater to a wide range of customers, and some need them. If you need
less, you can always leave them unused, but if you need more than are
available, you (and we) would have a serious problem.

DSP circuits can be used for many other functions than DSP.  :-)
Be patient...
Peter Alfke


Brannon King wrote:
> 
> So after looking at the Virtex4 line of devices and their associated
> features
> (http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
> little miffed at their chip resource allocation.
> 
> First of all, suppose I'm planning on filling an FPGA full of logic. I'm
> probably going to run the majority of that logic in the same clock domain so
> I don't need a whole lot of DCMs. However, I do need some way to get my data
> to/from the chip. What's up with zero transceivers on the "logic platform"?
> The same can be asked of the "signal processing platform". I was so looking
> forward to getting away from the old parallel I/O issues, and if I'm going
> to have to deal with that, maybe we better leave those DCMs on there. It
> wouldn't take very many transceivers to alleviate the issue.
> 
> Second, what about those of us who build and prototype digital bus
> controllers, routers, and similar applications. In that situation I'm
> looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs,
> a fair amount of logic, and not much else. DSP and Processors don't really
> help me in that type of application, yet to get what I need I will end up
> spending the extra money for the FX chip.
0
Reply Peter 6/10/2004 4:36:31 PM

I bet the answer you get from Xilinx will be along the lines of "we analysed
X number of designs from our customer base and found these three to be the
best fit (to maximise our profits)". They won't actually say the bit in
parentheses, but that's what they're in business for. Fair enough.
I guess the 'new' architecture makes it somewhat easier to add further
variants. After all, they've only used three letters (LSF) so far, that
leaves space for 23 more mixes! ;-)
I'm excited that the block structure will finally make partial
reconfiguration a reality.
cheers, Syms.


0
Reply Symon 6/10/2004 4:48:27 PM

Brannon,

Well, one can either say the glass is half full, or half empty.

In an extensive survey of customers, we organized the Virtex 4 family 
into the LX, FX, and SX.

The idea was pretty simple:  we have a lot of customers today who do not 
use the MGTs, and want more logic for less cost(LX).  They feel that 
they could have a lower cost solution if we did not put MGTs and 405PPCs 
in the chip (which they end up not using).

Then there are those that like the MGTs.  They have found that the MGTs 
go well with the 405PPCs, and those that like the PPCs often find use 
for the MGTs.  The logic and BRAM has to be sufficient to balance these 
applications out, so the FX family is targeted for those folks.

Then there are the DSP folks, (who quite frankly are happy with no one 
and nothing!).  They want humongous amounts of DSP specific 
functionality (logic?  who needs logic?).  The SX family is intended for 
them.  If we wished to add the MGTs to the SX family, then we have to 
ask, do they also need 405PPCs (as the two go together very well in 
talking to users).  Maybe they do?  Maybe they should?

Three major families.

If there is a significant demand for a hybrid of the feature sets, well, 
talk to us about it.  With ASMBL, it can be done without moving heaven 
and earth.  But remember that we supply a general purpose solution (now 
three general purpose solutions) so the chip has to have an almost 
universal appeal to a market segment, or it is not worth the effort to 
do it.

As for clocks, I am happy to hear you only use one clock, but consensus 
is that we need to supply more global (and local) clocks with increasing 
   numbers of CLBs to meet our customers' requirements.

Prototyping ASICs is no longer our "big" business.  In fact, it has 
gotten progressively smaller over the years as ASICs get progressively 
more difficult to do at all.  We love when people just have to have the 
largest parts we make, however.

If the mask for the next ASIC costs $2 million, then the cost (price) of 
the FX vs. the LX is not an issue anyway.

Austin

Brannon King wrote:
> So after looking at the Virtex4 line of devices and their associated
> features
> (http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
> little miffed at their chip resource allocation.
> 
> First of all, suppose I'm planning on filling an FPGA full of logic. I'm
> probably going to run the majority of that logic in the same clock domain so
> I don't need a whole lot of DCMs. However, I do need some way to get my data
> to/from the chip. What's up with zero transceivers on the "logic platform"?
> The same can be asked of the "signal processing platform". I was so looking
> forward to getting away from the old parallel I/O issues, and if I'm going
> to have to deal with that, maybe we better leave those DCMs on there. It
> wouldn't take very many transceivers to alleviate the issue.
> 
> Second, what about those of us who build and prototype digital bus
> controllers, routers, and similar applications. In that situation I'm
> looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs,
> a fair amount of logic, and not much else. DSP and Processors don't really
> help me in that type of application, yet to get what I need I will end up
> spending the extra money for the FX chip.
> 
> 
0
Reply Austin 6/10/2004 4:52:59 PM

"Brannon King" wrote:

>So after looking at the Virtex4 line of devices and their associated
>features
>(http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
>little miffed at their chip resource allocation.

Oh, everyone is miffed at chip resource allocation.  Almost always.
But for different reasons.  Just for a second, think about this from
Xilinx's point of view:

They can't make lots of different chips.  Each different type adds to
the development costs, support costs, inventory costs and sales costs.

Some of their customers need lots of (Pick one: RAM, IOs, DCMs,
processors, transceivers, multipliers, LUTS and FFs).  Many other
customers need less or could even care less.  For example, I've never
worked on a chip that had a reasonable use for a multiplier since the
XC4000 days, when there wasn't any multipliers!

So the chips Xilinx make must be compromises.  What I see in the
Virtex4 line is the following:

1) The logic platform is reasonable for things that are basically data
movers/processors with RAM buffers.  Yes, transceivers might be useful
for some, but parallel IO isn't dead yet, and will not be dead as long
as DDR SDRAM is the commodity memory technology.  Probably not enough
internal memory, but I'm sure there are other opinions!

2) The DSP platform is probably reasonable for DSP.  Perhaps someone
more versed in the DSP would could comment?

3) The full-featured platform should cover most other uses, but expect
to pay for features you don't need.

Now, did Xilinx miss any large volume uses of FPGAs?  I don't think
so.  Sure, a prototype router might require no hard processor, no
multipliers and other DSP support, and the designer will need to buy
the FX chip with these features, but how many of these are going to be
built?

YMMV, SRA, SDD, OMNHO, ...


--
Phil Hays
Phil_hays at posting domain should work for email

0
Reply Phil 6/10/2004 5:25:19 PM

Symon,

Ha ha ha.

That was really funny (really, it was).  Almost quoted me chapter and verse.

And I would hope it is OK with everyone that Xilinx continues to make 
money so that we can enable all of you to do likewise.

Glad you are not puzzled by any of this.

Austin

Symon wrote:
> I bet the answer you get from Xilinx will be along the lines of "we analysed
> X number of designs from our customer base and found these three to be the
> best fit (to maximise our profits)". They won't actually say the bit in
> parentheses, but that's what they're in business for. Fair enough.
> I guess the 'new' architecture makes it somewhat easier to add further
> variants. After all, they've only used three letters (LSF) so far, that
> leaves space for 23 more mixes! ;-)
> I'm excited that the block structure will finally make partial
> reconfiguration a reality.
> cheers, Syms.
> 
> 
0
Reply Austin 6/10/2004 6:08:37 PM

Hey,

Why so much negativity on this board regarding V4 already? It's the
most kick-ass and awesome FPGA ever made. How bout some kudos and a
big thanks to Xilinx for stepping up to the plate and hitting one out
of the park?

If you think the parts are not planned right or no thinking was put
into it you are on a different planet. The people with the most desire
for the right features determined the results. I really don't think
Xilinx told their customers what they need. So I would humbly submit
to you that if you don't understand the thinking, then you don't
understand the market.

Anyway, let's get a bit excited on this board about the most
significant advancement in FPGA technology in several years. It will
completely blow Stratix II and anything else out of the water in every
regard. Great thinking and innovation seem to be poured into V4.

500 MHz all over the place.
3 versions, Everything, logic, DSP
PPC 405
600 to 11 Gbps I/O
1 Gbps I/O on every pin

Sounds pretty spectacular to me. So get a bit excited and have some
positive thinking out there. V4 SX, LX, and FX are going to be the
standard in 90 nm FPGA technology.

Yeah!


"Brannon King" <bking@starbridgesystems.com> wrote in message news:<ca9v66$m5@dispatch.concentric.net>...
> So after looking at the Virtex4 line of devices and their associated
> features
> (http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=v4_asmbl), I'm a
> little miffed at their chip resource allocation.
> 
> First of all, suppose I'm planning on filling an FPGA full of logic. I'm
> probably going to run the majority of that logic in the same clock domain so
> I don't need a whole lot of DCMs. However, I do need some way to get my data
> to/from the chip. What's up with zero transceivers on the "logic platform"?
> The same can be asked of the "signal processing platform". I was so looking
> forward to getting away from the old parallel I/O issues, and if I'm going
> to have to deal with that, maybe we better leave those DCMs on there. It
> wouldn't take very many transceivers to alleviate the issue.
> 
> Second, what about those of us who build and prototype digital bus
> controllers, routers, and similar applications. In that situation I'm
> looking for an FPGA with lots of memory, lots of transceivers, lots of DCMs,
> a fair amount of logic, and not much else. DSP and Processors don't really
> help me in that type of application, yet to get what I need I will end up
> spending the extra money for the FX chip.
0
Reply seannstifler69 6/11/2004 6:14:07 AM

Can you point me to some technical data on the enhanced partial
reconfig capabilities?  I'm very interested in this area and I can't
seem to find anything on Xilinx's site that wasn't written by somebody
from the marketing department.

  - a

"Symon" <symon_brewer@hotmail.com> writes:
> I bet the answer you get from Xilinx will be along the lines of "we analysed
> X number of designs from our customer base and found these three to be the
> best fit (to maximise our profits)". They won't actually say the bit in
> parentheses, but that's what they're in business for. Fair enough.
> I guess the 'new' architecture makes it somewhat easier to add further
> variants. After all, they've only used three letters (LSF) so far, that
> leaves space for 23 more mixes! ;-)
> I'm excited that the block structure will finally make partial
> reconfiguration a reality.
> cheers, Syms.
>
>

-- 
"The first time I read this book I felt what I could only explain as a
 great disturbance in the Force: it was as if a billion washing
 machinces all became unbalanced at once and were suddenly silenced."

                             -- anonymous book reviewer on Amazon.com
0
Reply Adam 6/11/2004 8:28:20 AM

"Stifler" <seannstifler69@hotmail.com> wrote in message
news:bf780a06.0406102214.3bc26509@posting.google.com...
> Hey,
>
> Why so much negativity on this board regarding V4 already? It's the
> most kick-ass and awesome FPGA ever made. How bout some kudos and a
> big thanks to Xilinx for stepping up to the plate and hitting one out
> of the park?

Has it been made yet?  I was real happy to see the announcement but a bit
disappointed that it didn't come with some data sheets for a good
architectural description with all the minutia about resources available in
the planned parts.  I'm okay with not having working silicon for a short
while but I think some of the backlash on this board was because of the
insensitive tease.  Bait the engineers with something that looks very good
but don't give them any real meat.  I'm looking forward to further news.

> If you think the parts are not planned right or no thinking was put
> into it you are on a different planet. The people with the most desire
> for the right features determined the results. I really don't think
> Xilinx told their customers what they need. So I would humbly submit
> to you that if you don't understand the thinking, then you don't
> understand the market.
>
> Anyway, let's get a bit excited on this board about the most
> significant advancement in FPGA technology in several years. It will
> completely blow Stratix II and anything else out of the water in every
> regard. Great thinking and innovation seem to be poured into V4.

You may be overstating a bit to suggest this is "the most significant
advancement" since the features are almost everything we've already seen.
The PPC, the MGT, the CLB structure (I believe) are all pretty much the
same.  The evolutionary features that are attractive include the enhanced
DSP elements including hardware divide and the no-overhead FIFO mode for the
BlockRAMs.  Neat stuff, but it doesn't come across as a revolutionary
product.  Evolutionary is fine.

Didn't Stratix-II come out with a "revolutionary" change to the LUT
structures to allow interesting input configurations such as independent
3-bit and 5-bit input functions without chewing up other resources?  A
little flexibility is a good thing.  Don't get me wrong - I like the LUTs we
get from Xilinx thanks to the memory and SRL capabilities;  I've used them
virtually unchanged for years and years.

> 500 MHz all over the place.
> 3 versions, Everything, logic, DSP
> PPC 405
> 600 to 11 Gbps I/O
> 1 Gbps I/O on every pin

A nice feature set, indeed.

> Sounds pretty spectacular to me. So get a bit excited and have some
> positive thinking out there. V4 SX, LX, and FX are going to be the
> standard in 90 nm FPGA technology.
>
> Yeah!

I'm hoping Xilinx continues to deliver the price/performance advantages
we've come to enjoy.
Looking forward to it!


0
Reply John_H 6/11/2004 3:44:12 PM

Symon wrote:
> 
> I'm excited that the block structure will finally make partial
> reconfiguration a reality.

I missed something.  I don't see anything that talks about partial
reconfiguration and what I do see indicates these parts are still
designed around columns.  

I am still waiting for modular configuration support for Spartan 3.  I
was told over six months ago that they had just a couple of issues that
needed to be addressed before they could provide this and that Xilinx
was commited to providing this feature.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
0
Reply rickman 6/11/2004 4:12:41 PM

Adam,
I don't know any technical details, but it struck me that the block
structure is ideally suited to partial reconfiguration on a block by block
basis. It's like lots of mini FPGAs on one die, much more than it was
before. I don't believe that Xilinx will pass up this opportunity to tune
the software to allow block by block P&R etc. I envisage an application, a
bit like Ultracontroller, that demonstrates 'partial configuration for
dummies' of a ASBL block with a standardised interface to adjacent blocks.
I'd recommend pestering your FAE, if enough people are interested or, more
importantly, enough people will use this feature, I'm sure the marketing
machine will respond! From my point of view, with an FPGA with as many gates
as these parts will have, I think partial reconfiguration will become the
norm as more and more little ASICs are converted to IP and hoovered up into
the FPGA.
cheers, Syms.

"Adam Megacz" <adam@megacz.com> wrote in message
news:m13c521ot7.fsf@nowhere.com...
>
> Can you point me to some technical data on the enhanced partial
> reconfig capabilities?  I'm very interested in this area and I can't
> seem to find anything on Xilinx's site that wasn't written by somebody
> from the marketing department.
>
>   - a


0
Reply Symon 6/11/2004 4:17:37 PM

Rick,
I'm so excited that maybe my grammar got away from me. Try replacing
'excited' with 'optimistic' to get what I meant. The 'new' thing that Xilinx
is pushing is this ASBL block structure. Surely(!?) they've designed these
blocks to be easily individually programmable? Especially as valued
customers like us have been pushing for it for years?
Cheers, Syms.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:40C9D9F9.E6D04ADB@yahoo.com...
> Symon wrote:
> >
> > I'm excited that the block structure will finally make partial
> > reconfiguration a reality.
>
> I missed something.  I don't see anything that talks about partial
> reconfiguration and what I do see indicates these parts are still
> designed around columns.
>


0
Reply Symon 6/11/2004 4:45:43 PM

I would be willing to bet NOT.  I don't see any sign that the ASBL
blocks relate to configuration blocks.  Yeah, it would be a great think
if they could do that, but I'm not holding my breath.  


Symon wrote:
> 
> Rick,
> I'm so excited that maybe my grammar got away from me. Try replacing
> 'excited' with 'optimistic' to get what I meant. The 'new' thing that Xilinx
> is pushing is this ASBL block structure. Surely(!?) they've designed these
> blocks to be easily individually programmable? Especially as valued
> customers like us have been pushing for it for years?
> Cheers, Syms.
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:40C9D9F9.E6D04ADB@yahoo.com...
> > Symon wrote:
> > >
> > > I'm excited that the block structure will finally make partial
> > > reconfiguration a reality.
> >
> > I missed something.  I don't see anything that talks about partial
> > reconfiguration and what I do see indicates these parts are still
> > designed around columns.
> >

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX
0
Reply rickman 6/11/2004 5:45:00 PM

The real question is not if the support partial reconfiguration ... but you
and how many others want it... there was a partially configurable Xilinx
....once .. many years ago... but it came and went.. this is capitalism not
fantasy money talks the rest walk.
So unless someone is willing to spend $$$ partial reconfiguration is an
electric dream. and if you really need it.. put down 2 devices :-)

Simon


"Symon" <symon_brewer@hotmail.com> wrote in message
news:2iu5tqFqvetqU1@uni-berlin.de...
> Rick,
> I'm so excited that maybe my grammar got away from me. Try replacing
> 'excited' with 'optimistic' to get what I meant. The 'new' thing that
Xilinx
> is pushing is this ASBL block structure. Surely(!?) they've designed these
> blocks to be easily individually programmable? Especially as valued
> customers like us have been pushing for it for years?
> Cheers, Syms.
> "rickman" <spamgoeshere4@yahoo.com> wrote in message
> news:40C9D9F9.E6D04ADB@yahoo.com...
> > Symon wrote:
> > >
> > > I'm excited that the block structure will finally make partial
> > > reconfiguration a reality.
> >
> > I missed something.  I don't see anything that talks about partial
> > reconfiguration and what I do see indicates these parts are still
> > designed around columns.
> >
>
>


0
Reply Simon 6/12/2004 5:31:07 AM
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In profiling it is typical that some few lines of the code take a major part of the total execution time. Graphically like this( letters a program part names, numbers time consumed in time units) : A: 0000000000 1111111111 2222222222 3333333333 4444444444 555555555 666 B: 0000000000 1111111111 2222222 C: 0000000000 1 D: 000 E: 00 F: 0 G: 0 H: 0 I: J: K: L: M: N: If one tries to reduce to execution time it is useful to concentrate to A, and perhaps to B, C but forget D..N totally. This is probably a trivial fact for every reader when talking about program execution time or memory usage....

Thinking of buying from Basshome .com
Basshome.com is operating with an **EXPIRED** Verisign certificate. It expired on October 28, 2003 You can see that HERE:http://tinyurl.com/t43e Read about what happened to this DIY using his credit card at http://www.bass-home.com Read the story here: http://goofysplace.com/cust3.htm Read more about the owner/operator of bass-home.com HERE: http://goofysplace.com/testimony.htm ...

If you think you must modify the hash, think again
As I've said before, if you find yourself leaning towards a design that modifies the location hash because you think that an app can't be "modern" or "robust" or "fast" without such hack-ery, think again. There's always a better design (and often it involves leveraging what the browser does best, which is _browsing_). I ran across this recently:- http://stackoverflow.com/questions/1078501/keeping-history-of-hash-anchor-changes-in-javascript It is a microcosm for everything that has gone wrong with "Web 2.0" (quotes indicate that...

Thinking Factor beats Thinking Forth
On physical page 71 of the pdf file, Brodie presents a problem. All charges are computed by the minute, according to distance in hundreds of miles, plus a flat charge. The flat charge for direct dial calls during weekdays between 8 A.M. and 5 P.M. is .30 for the first minute, and .20 for each additional minute; in addition, each minute is charged .12 per 100 miles. The flat charge for direct calls during weekdays between 5 P.M. and 11 P.M. is .22 for the first minute, and .15 for each additional minute; the distance rate per minute is .10 per 100 miles. The flat ch...

Think your Wireless Network is Secure? Think Again.
The greatest problem with 802.11 security is that it is usually not implemented properly. http://www.safeit.ca/wireless.htm Check it out! Keep your Private network Private. -- Wojtek Network Security Consultant www.SafeIT.ca "We make your network security our business, so you can get on with yours." --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.567 / Virus Database: 358 - Release Date: 24/01/2004 ...

What to think about this?
Hello poeple, Maybe some of you had similar experiences: 2 Months ago, I bought 2 HP-49G+. While using one, I kept the other in its box for my collection. After one month of use, the screen shown me a malfunctionning: 2 vertical lines on the left side of the screen were not displayed. So, I came back to the shop where I bought it and they changed the machine which was under warranty. I opened the one I kept for my collection, and used it for a mont. But today, I had a strange keyboard behaviour: the [ON] key was simply broken. Same thing, I came back to the shop again and they changed m...

Understanding ++
Could someone help me understand this: { int i=3D-3,j=3D2,k=3D0,m; m=3D++i && ++j || ++k; } { int i=3D-3,j=3D2,k=3D0,m; m=3D++i || ++j && ++k; } What are the final values of variable in both cases, and how? TIA. yes@yes.yes spoke thus: > { > int i=-3,j=2,k=0,m; > m=++i && ++j || ++k; > } && has precedence over ||, so this is equivalent to m=(++i && ++j) || ++k; Assuming you didn't forget a loop or something, you get m=(-2 && 3) || 1; so m=1 (true), i=-2, j=3, and k=1. > { > int i=-3,j=2,k=0,m; > m=++...

Do not understand this
I am going through Dave Thomas's Programming Ruby Second Edition book. I am trying to execute the code given on page 89 of the book which is as follows: # Sample code from Programing Ruby, page 83 alias old_backquote ` def `(cmd) result = old_backquote(cmd) if $? != 0 fail "Command #{cmd} failed: #$?" end result end print `date` print `data` when I try to run this code by typing ruby ex200.rb at the command prompt (on Windows XP machine), the program hangs. When I abot it by hitting CTRL-C key combination, I get the following stack-trace: ex02...

how can we think mathematics is a tool to simularte our thinking
Hello everybody 1. Suppose a stream of info enters us. Do we know all what enters us. Don't we meet surprises? 2. Our brain processes the stream and changes physically, maybe we react. 3. A second stream not completely known as well enters. But in what kind of brain when it changes all the time and how will we react then. Can't we do strange things? The underlying factor is this. 4. when the teacher in a kindergarten offers a nice cookie jar to all the children. What will those children do then. What do you think. Oh certainly that have enough abilities. But those are like circu...

How we think in Sw......extension to New thinking in SW
I am starting this thread over because the other one is so congested with BS that sorting through it gives me a head ache. So this is for any of you CAD junkie out there that would like to post up about new ways that you have started using the program because of some of the new tool. How it may or may not effect/hinder you work flow. > For me, the new multibody feature in 2003 is the most useful > new tool I've ever come across. I use it all the time! > > Regards, > Mike Wilson Yep, seconded. The new part manipulation workflow within assemblies on 04 is a LOT nicer, too ...

what do you think, why that?
it only displays the name, but the last name and the address seems not to exist! why? <?php @ $db=mysql_pconnect('host', 'UserID', 'PWD'); if (!$db) { echo 'conneciton eror'; exit; } else { echo 'connection on!'; } mysql_select_db('list'); $query="select * from index"; $result=mysql_query($query); $num_results=mysql_num_rows($result); if ($num_results == 0) { echo'<br><br>nothing to dispaly'; } else { echo'<br><br>here are the results: '.$num_results; } for ($i<0; $i<$num...

What do you think?
I tried putting a Gateway 7422 GX notebook through a large and powerful sound system and got all sorts of hard drive noise along with the music. I connected a Sony notebook the same way and it was quiet, no background noise at all just music. Why would there be such a difference in notebooks? The Gateway is the newer system. Dave nhsinglesparties@verizon.net David McDermott wrote: > I tried putting a Gateway 7422 GX notebook through a large and > powerful sound system and got all sorts of hard drive noise along > with the music. I connected a Sony notebook the same way and...

What do you think?
Please give me your opinion! I have a database that BEFORE splitting can open 25-30 forms at once before getting the message: Run-time error '3048' Cannot open anymore databases. After splitting the database I can only open 5-7 forms before getting the same message. I think it may have something to do with using code like: Dim qdf As QueryDef Set qdf = CurrentDb.QueryDefs("chtPositionLevel") qdf.Close Instead of using code like: Dim qdf As QueryDef Dim db As Database Set db = CurrentDb Set qdf = db.QueryDefs("chtPositionLevel") qdf.Close db.Clo...

how to understand
#object.c: Init_Object() { rb_cObject = boot_defclass("Object", 0); rb_cModule = boot_defclass("Module", rb_cObject); rb_cClass = boot_defclass("Class", rb_cModule); } =======boot_defclass======== boot_defclass(name, super) { VALUE obj = rb_class_boot(super); } ========rb_class_boot======== rb_class_boot(super) { OBJSETUP(klass, rb_cClass, T_CLASS); } #################################### when call "boot_defclass("Object", 0)","rb_cClass" is not defined,why "rb_class_boot" can call "rb_cClass"...

What do you think ?
Hello all ! I use hp49g+ but I would like to know the stack better and to write programs. I found this book in Samson Cables and would like to hear your opinion about it. Is it worth the money or I can find more information on the net. Has anyone read this book ? this is the the link : http://www.samsoncables.com/catalog/prodDetail.cfm?Prod_ID=215&Sku=0931011418 Thanks, Idan idan wrote: > Hello all ! > > I use hp49g+ but I would like to know the stack better and to write > programs. > I found this book in Samson Cables and would like to hear your opinion > about it...