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Xilinx FIFO Flag Question

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I generated a 32-bit by 1024 entry FIFO using the FIFO Generator.  The
FIFO is an independently-clocked BRAM that has a 39 MHz clock on the
write side and a 100 MHz clock on the read side.

I am writing one 32-bit entity to the FIFO from the write side.  The
empty flag takes > 50 clock cycles on the read side to deassert.  I
would think that the empty flag would go low much sooner.  Again, the
FIFO is implemented as independent read/write clocks and I am using
the structural simulation file.  I need empty to go low much sooner
than this.
0
Reply mottoblatto (48) 10/16/2007 1:59:55 AM

comp.arch.fpga 18348 articles. 19 followers.

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