I've built my own Xilinx parallel cable as described here:
My version is here: http://cjoint.com/?gttCeFju7q (Vdd is adjusted so
that Vcc is 5V exactly).
Unfortunately, it does not work even after electrical checks. After
lauching "cable autodetect" (I've tried 2 ways: programmer connected to
a custom minimalist xc9536 board and programmer only connect to power,
the cable length should not be important to detect to programmer(?) ):
"Connecting to cable (Parallel Port - LPT1).
Checking cable driver.
Driver windrvr6.sys version = 220.127.116.11. LPT base address = 0378h.
ECP base address = 0778h.
Cable connection failed."
Since it does not work in Impact software (available in webpack 7.1i
under Win2000) I have a couple of questions to ask:
- should the parallel cable be detected by Impact when it is only
connected to power (JTAG pins are left unconnected) or is it absolutely
necessary to connect it to a CPLD/FPGA?
- my parallel port settings under BIOS and Win2K are "ECP DMA:3" is this
correct (EPP needed?)?
- Impact allows to manually select the cable, is this a parallel cable
III or IV?
- in this schematics, could 74HC125 be replaced by 74LS125?
- how is it possible to test the cable without FPGA/CPLD hardware?
PS: I don't want to buy any programmer neither build a programmer with
different schematics since it should work, I would like to learn from my
hardware building errors.
||6/19/2005 5:45:25 PM