f



XILINX slice structure detaild description

Hi
I would like to know if any of you knows a good paper (app note etc.)
that describes the xilinx slice sturcture in details, I know the
general cell architecture (e.g. - two LUTs, Two regs and carry logic)
but I wanted to get a lot more fimiliar with the architecture and
functionally of each logic element in the cell, for example how exactly
does the carry logic is structured etc.

The reason for this qeustion is that I want to implement arithmetic
block using as less logic and routing as possible
I wonder if there is an application note that explains how to code and
route your arithmetic functions in a way that is best suitable for the
xilinx chip (spartan 2E).

So if any of any of you is fimiliar with such a paper I will be
grateful for a link.

Regards
MC

0
MC
12/15/2004 10:22:02 AM
comp.arch.fpga 18545 articles. 2 followers. Post Follow

1 Replies
599 Views

Similar Articles

[PageSpeed] 5

MC wrote:

>Hi
>I would like to know if any of you knows a good paper (app note etc.)
>that describes the xilinx slice sturcture in details, I know the
>general cell architecture (e.g. - two LUTs, Two regs and carry logic)
>but I wanted to get a lot more fimiliar with the architecture and
>functionally of each logic element in the cell, for example how exactly
>does the carry logic is structured etc.
>
>The reason for this qeustion is that I want to implement arithmetic
>block using as less logic and routing as possible
>I wonder if there is an application note that explains how to code and
>route your arithmetic functions in a way that is best suitable for the
>xilinx chip (spartan 2E).
>
>So if any of any of you is fimiliar with such a paper I will be
>grateful for a link.
>
>Regards
>MC
>
>  
>
No need to study a paper on this.  Open the FPGA editor tool.  All the 
information you need is there.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759


0
Ray
12/15/2004 2:22:37 PM
Reply:

Similar Artilces:

fpga board with audio in/out (xilinx fpga) ?
Hello I'm searching for a FPGA board for about $500 with an "audio in" and "audio out" port... adequate for audio processing applications. I thought of a Virtex II fpga, but can be another one from XILINX.... Can anyone recommend a board like this ? Regards, Timo Dammes "Timo Dammes" <timo.dammes@gmx.de> wrote in news:cdghf4$1gq$1@nx6.HRZ.Uni-Dortmund.DE: > Hello > > I'm searching for a FPGA board for about $500 with an "audio in" and > "audio out" port... adequate for audio processing applications. I > thou...

Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?
Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable? No. On Apr 26, 11:41 pm, mohan <kulka...@math.net> wrote: > Can i programme non-xilinx fpga through xilinx impact tool & by using > xilinx parrellel four cable? Using their cable? Sure, you just need software to drive it. You might have to operate it in a slower bit bang sort of mode. Using impact? maybe, but it won't be easy. If you can get the data and algorithm into a generic form that impact will execute, such as maybe an SVF, you might be able to do it that w...

structures, structures and more structures (questions about nested structures)
Hi, I have the ff data types : typedef enum { VAL_LONG , VAL_DOUBLE , VAL_STRING , VAL_DATASET }ValueTypeEnum ; typedef union { long lval ; double fval ; char* sval ; void* ptr ; } Value ; typedef struct { int magic ; int version ; }Header ; typedef struct { char label[20] ; id int ; }Key ; typedef struct { Header *hdr ; char *subject ; int subject_len ; Key key ; ValueTypeEnum type ; Value value ; int text_len ; int size ; }MotherStruct ; If I have a variable declared as ff: MotherStruct *pMS = calloc(1,sizeof(MotherStruct*)) ; 1). Do I have to al...

Can I implement a Labview FPGA Program on a Xilinx FPGA ?
Hi, &nbsp; I'm actually working on a Xilinx program in VHDL. I'd wish to begin again a part of this program, and it will be easier for me to create it with Labview FPGA. My idea is to create a sub program in my existing VHDL program, and make this sub program thanks to Labview FPGA. I know we can't get the VHDL code create by Labview to download it on another FPGA (because Labview FPGA is only for use on Xilinx). But I'd wish to download my program on a Xilinx Virtex 2 Pro. So, is there a solution to integrate my Labview FPGA program as a sub program in my VHDL code (for a ...

about slices in xilinx
hi all, i have a doubt regarding no.of slices in xlinx what are slices? what are LUT? in xilinx 1)the no.of slice constant in every version or does it vary? 2)can the area of an architecture be decreased if we say no.of slices are decreased. is this type of approach is correct? or 3) how can we say a area of architecture is decreased? 4)i am implementing project which is having the no.of slices in order of hundreds. where as the previous technique implemented have the no.of slices in order of thousands from this can we conclude that the area is decreased. please kindly answer. my...

FPGA+xilinx
Do anyone know the procedure of installing the system generator. please do reply ...

Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
Hello all, knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can I convert this into a Xilinx CPLD Macrocell? Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD Device (number of Macrocells) would be sufficient? Haven't found any reference at xilinx or google. Thanks for any feedback, Richard "Eric" <ca9@gmx.de> wrote in message news:LeCdnY3PC6QpebvUnZ2dnUVZ_uidnZ2d@giganews.com... > Hello all, > > knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can > I convert this into a Xilinx CPLD Macr...

What is the diffrences between lattice's FPGA and Xilinx's FPGA
Regards: What is the diffrences between lattice's FPGA and Xilinx's FPGA Thank You. Best Regards to you all. On 20 Aug 2005 11:02:04 -0700, mikelinyoho@gmail.com wrote: >Regards: > > What is the diffrences between lattice's FPGA and Xilinx's FPGA Lattice FPGAs are made by Lattice at http://www.latticesemi.com/ Xilinx FPGAs are made by Xilinx at http://www.xilinx.com/ There are 7 letters in Lattice There are 6 letters in Xilinx If you want better answers, you need to ask better questions. Let me help you: Tell us what research you have already ...

Xilinx FPGA, OFFSET OUT AFTER
hi, I want to operate the XILINX Virtex-4 XC4VLX60(Speed -12) at a frequenz of 130 MHz. So i write the following constraints to my UCF(user constraint files). NET "i_clk_adc" PERIOD = 6 ns HIGH 50 %; # clock periode, 6ns(about 160MHz) OFFSET = IN 3 ns BEFORE "i_clk_adc" HIGH ; # Input signal must be ready, 3 ns before rising edge OFFSET = OUT 5 ns AFTER "i_clk_adc" HIGH ; # Output signal must be at the PAD, 5 ns after the rising edge. However, the constraints OFFSET = OUT 5 ns AFTER "i_clk_adc" HIGH ; cannot be met. Actual timing is ab...

Doubts on Xilinx FPGA
Hello all, Is there any way i can initialise values into the Xilinx FPGA FF. I am working on the Virtex E FPGA. Please tell me how can i achive that through verilog. Thank you Any flip-flop that has an asynchronous reset or preset term will be initialized automatically when the FPGA is loaded from the bitstream. The standard templates for flip-flops are available in the Language Templates options of ISE. Menu: Edit --> Language Templates... Navigate to: Verilog --> Synthesis Templates --> Flip Flops --> D Flip Flop with Asynchronous Reset This shows the standard template f...

Xilinx FPGA + SMPS
Is there any known pitfalls or problems with driving xilinx fpga (spartan) with smps (buck) ..? sky465nm@trline4.org wrote: > Is there any known pitfalls or problems with driving xilinx fpga > (spartan) with smps (buck) ..? Yes, not reading the "Troubleshooting hints" section of AN19 first. Particularly hint 12. Google :- AN19 site:linear.com HTH., Syms. Go here: http://www.xilinx.com/products/design_resources/power_central/ Then scroll down to the manufacturers. Pick the one you like, and go to their Xilinx FPGA power supply pages. All choices are "approved&...

Xilinx Slice and Altera ...?
Hi Sorry to bother the group with something I really should have been able to figure out myself, but I'm sort of pressed for time, so I hope you bear with me. I have some (limited) knowledge of the (modern) Xilinx Virtex 'Slice', and how it is constructed, so to speak. But how similar is the Altera FPGAs' building blocks, and what are they called? Oh, and how, if at all, similar are the two? Panic wrote: > > Hi > > Sorry to bother the group with something I really should have been able to > figure out myself, but I'm sort of pressed for time, so I hop...

90nm Xilinx FPGA?
**** Post for FREE via your newsreader at post.usenet.com **** Ref: http://www.physorg.com/news180.html -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= *** Usenet.com - The #1 Usenet Newsgroup Service on The Planet! *** http://www.usenet.com Unlimited Download - 19 Seperate Servers - 90,000 groups - Uncensored -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= ...

XILINX FPGA project
I am required to design and demonastrate a project incorporating the XILINX Field Programmable Gate Array Board already assembled by Digilent Inc. The circuit will require some extra components other than the XILINK chip but as our knowledge is not in the advanced stages of PLA's yet, the project will not need to be overly complex. Any ideas, pointers or common industry practice for implementing the use of a FPGA to utilize and demonstrate its benefits would be welcomed - just a point in the right direction..... Regards Dave ...

Web resources about - XILINX slice structure detaild description - comp.arch.fpga

Active Format Description - Wikipedia, the free encyclopedia
In television technology, Active Format Description ( AFD ) is a standard set of codes that can be sent in the MPEG video stream or in the baseband ...

‘Impressum’ Added To Facebook Page Descriptions For Some Pages In Italy?
... are being prompted to add an “impressum” — or a legally mandated statement of the ownership and authorship of a document — to their page descriptions. ...

In the recent transition, the Scripting News feed lost its descriptions. Fixed. ;-)
In the latest transition on "Scripting News" a bug appeared that caused my feed to lose its descriptions on new posts. This has now been fixed. ...

META Description - Flickr - Photo Sharing!
www.seroundtable.com/archives/016691.html

Le Mans 1955 accident: Raw footages of the crash in HD (Read description) - YouTube
Visit http://trajectoires.net to watch the preview of my project: Le Mans 1955 accident raw footages. This accident was captured at least on ...

Glenn O’Brien’s Ideal Job Description
It takes flair and a certain amount of years in the media business to execute the following maneuver , during an informal job interview, with ...

"Now, what could possibly be wrong with the description 'hard worker'?"
Asks Greta Van Susteren before playing video of Melissa Harris-Perry calling out a guest for saying that Paul Ryan is a "hard worker." This is ...

A male model has a blunt description of his beauty routine
Felix Gesnouin isn't your typical model. He has an off-the-wall Instagram account , and once told Details the best advice he's ever gotten is, ...

See Police Sketches Of Literary Characters Made Using Book Descriptions
The Composites Tumblr reveals what police sketches of famous literary characters would look like if the artist only had the books to go on.

An Angel Investor's Job Description
Being an angel investor has a certain cache. You’re sought after by entrepreneurs and assess the value of their ideas. You choose whether or ...

Resources last updated: 1/24/2016 3:23:41 PM