**about slices in xilinx**hi all,
i have a doubt regarding no.of slices in xlinx
what are slices?
what are LUT? in xilinx
1)the no.of slice constant in every version or does it vary?
2)can the area of an architecture be decreased if we say no.of slices are
decreased.
is this type of approach is correct?
or
3) how can we say a area of architecture is decreased?
4)i am implementing project which is having the no.of slices in order of
hundreds.
where as the previous technique implemented have the no.of slices in order
of thousands from this can we conclude that the area is decreased.
please kindly answer.
my...

**Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell**Hello all,
knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can
I convert this into a Xilinx CPLD Macrocell?
Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD
Device (number of Macrocells) would be sufficient?
Haven't found any reference at xilinx or google.
Thanks for any feedback,
Richard
"Eric" <ca9@gmx.de> wrote in message
news:LeCdnY3PC6QpebvUnZ2dnUVZ_uidnZ2d@giganews.com...
> Hello all,
>
> knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can
> I convert this into a Xilinx CPLD Macr...

**Xilinx multiplier out of slices**Hi,
I'm new to the Xilinx tools. How do I tell Xilinx ISE 7.1 to synthesise
the following statement:
y <= a * b;
to NOT use dedicated multipliers?
Thanks a bunch, Pete
Pete,
Synplify uses an attribute called syn_multsyle. I know this doesn't answer
your question but it might help in your google searches?
Good luck, Syms.
"Peter Sommerfeld" <psommerfeld@gmail.com> wrote in message
news:1114204591.770429.197140@z14g2000cwz.googlegroups.com...
> Hi,
>
> I'm new to the Xilinx tools. How do I tell Xilinx ISE 7.1 to synthesise
> the following statemen...

**Xilinx Slice and Altera ...?**Hi
Sorry to bother the group with something I really should have been able to
figure out myself, but I'm sort of pressed for time, so I hope you bear with
me.
I have some (limited) knowledge of the (modern) Xilinx Virtex 'Slice', and
how it is constructed, so to speak. But how similar is the Altera FPGAs'
building blocks, and what are they called?
Oh, and how, if at all, similar are the two?
Panic wrote:
>
> Hi
>
> Sorry to bother the group with something I really should have been able to
> figure out myself, but I'm sort of pressed for time, so I hop...

**gate/xilinx slice**Hi,
What is the usual ratio to know how many gate does a design represent when
we get the number of xilinx slice needed??
Regards,
Alexis
kcl wrote:
> Hi,
>
> What is the usual ratio to know how many gate does a design represent
when
> we get the number of xilinx slice needed??
>
> Regards,
>
> Alexis
Here we go again...
There have been many discussions on design gate equivalents and
how the "gates" in a part relate between manufacturers. You can't
really relate the slice count in a design to gates, because the
gate count depends on what resour...

**How to introduce delay in Structural description ?**Hi all,
The follwing code is simple 2-input and gate model.
Here I am having doubt.
begin
t1 : and4 port map ( in1, in2, out1 );
t2 : and_output port map ( out1,out2);
end and_arch ;
I know these two instance t1,t2 will be executed concurrently at 0 ns
simulation time.But here T1 instance will execute at 0ns simulation
time.t2 instance will execute after updated the value from out1.So Here
I need to introduce some delay to execute the t2 instance at some
simulation time.
How to introduce delay at instance t1? Give me some ideas to proceed
further?
regards,
priya
-------...

**VHDL description of an array structure**Hi,
I'm writing VHDL code to describe a system of which the structure is an
array of some building blocks.The inputs and outputs of such a building
block may be about 10 bits wide.And there will be around 100 of these
building blocks in the structure.So is there a smart way to do this
instead of instantiating every one of them and porting map them
together?coz otherwise it'll be a lot of copy-paste and quite
error-prone.
panthera
panthera wrote:
> Hi,
>
> I'm writing VHDL code to describe a system of which the structure is an
> array of some building blocks.The inp...

**Data structure for Earth slice data**I'd like to use Mathematica to solve this problem:
What's a good data structure/methodology for representing "slices" of
the Earth?
More specific example: the set of points that are less than 1600 miles
from Chicago AND less than 1000 miles from Albuquerque AND less than
800 miles from Dallas.
Obviously, the description above is one way to represent the data, but
it's not very useful.
I want a representation that will:
% Tell me if a given latitude/longitude is inside or outside the set.
% For a given latitude, tell me what longitudes (if any) are ...

**Misleading description of [i:j:k] slicing?**As of Python 2.3, Section 2.2.6 (Sequence Types) describes slices
which have a specified step (to omit some indexes in beteween), using
the notation s[i:j:k]. The note about how this works says:
"The slice of s from i to j with step k is defined as the sequence
of items with index x = i + n*k such that 0 <= n < abs(i-j). [...]"
Seems to me that "0 <= n < abs(i-j)" is wrong, since the range of n
gets multiplied by k. I would suggest that it should be something
like:
"x = i + n, such that n is a multiple of k and 0 <= n < abs(i-j)"
or maybe...