New High Bandwidth Supercomputer

http://www.eetimes.com/electronics-news/4206456/IBM-describes-Power7-supercomputer Maybe all you whiners out there will like this one. :-) The video link in the article doesn't seem to work. I'll have to see if I can locate it.

Renamer Port Reduction

I tried to find Mitch's post to reply to, but my newsreader, Thunderbird, is not cooperative. So I'll have to swag it: Mitch Alsup a little while back said something like "It isn't the ports on the register file that are a problem, it's the ports on the renamer." With, IIRC, a comment that you had to squeeze the renamer into a single pipestage. Not true. This reminds me of a comment by Tim Olson, then of AMD (and active on comp.arch), when I presented HaRRM, my Hardware Register Renaming Mechanism (which is basically the modern form of renaming) to him. He said that it

Turing Machine versus parallel programming

Turing specified the mathematical basis of single threaded programming. His machine was as a practical solution useless but it was a magnificent example of maths setting the basis of the whole concept of calculating computability. Has anyone actually asked a pure mathematician to try to produce a mathematical model for parallel computing. Ken Young

Disadvanteges of Windowed Register File (like Am29k)

I am thinking about an architecture for a processor mainly targeted for implementation in FPGAs (but also with non-FPGA applications in mind). I came up with a variable size windowed register file, just to realize that something similar was already implemented in the Am29000 family. (Damn, another good idea, 25 years too late...) Now I am curios why this IMHO superior concept did not have more impact. The arguments against it that I found by googling were not very convincing. Beside the advantage of fast function-calling, are there any real disadvantages (assuming that the window-siz

AMD retires 3DNow! instruction set

I think it's good that somebody isn't afraid to remove support for certain legacy instruction sets in the x86 world. It's not that software will fail because of it, since the proper way to implement support for it was to check its flag with the CPUID instructions. Yousuf Khan *** HEXUS.net - News :: AMD retires 3DNow! instruction set : Page - 1/1 "There are two commands that will survive the retirement, though, and those are PREFETCH and PREFETCHW. AMD is integrating these commands into a class of their own and will continue to include them in future CPUs." http://www.he

OOO and Branch prediction

Sorry but my programming days were back in the 8 bit days. Is their a simple explanation of how OOO and Branch prediction work and the advantages of these? Pipelines in in-order machines I think I understand. Ken Young

IBM Daisy (VLIW binary translation project) source download?

Hi, I'm trying to access the source code of IBM's Daisy project. While the project web pages are still available at http://www.research.ibm.com/daisy/, the download link http://oss.software.ibm.com/developerworks/opensource/daisy redirects to a generic IBM open source page which does not mention the Daisy project. So, I'm looking for a working download link (Google didn't help) or a copy of the source code from someone who happened to save it... anyone? Best regards, Michael

Cost of moving data and the power budget

This chart http://www.coherentlogix.com/index.php?option=com_content&view=article&id=48&Itemid=67 made me wonder, as usual, how one would feed such a beast, but it also made me wonder if the power consumed by processing (performance/ processor-watt) matters all that much any more, and in what contexts. In general, I would expect the power budget for high-throughput processing to be dominated by the cost of moving data and not the cost of crunching it. I assume that the answer would be signal processing applications, about which I know very little in practice. Can someone offe

Alphabet_Soup:_a_Collection_of_Microarchitectures

Attempting to describe some microarchitectures in text-only email to a friend inspires me to post this. It would be much better to have lots of drawings illustrating precisely what I am talking about; but this textual notation is fairly compact, can be understood by some people, and in some ways, because it underspecifies certain configurations, allows us to talk without getting bogged down in multiple different ways of interconnecting the blocks. I.e. sometimes drawing is TOO specific. = Basic Pipelines = Let's start out with in-order pipelines InO and out-of-order pipel

Obvious coherence filter idea?

Might it not make sense to use different granularity bloom filters for coherence filtering? (I have read suggestions of using bloom filters in coherence and having page-granularity coherence, so merging the two seems obvious--especially given the multiple-hash nature of bloom filters.) Unfortunately, I cannot think of a good way to maintain a page-grained filter given the cache-block granularity of most coherence. One could count cache blocks, perhaps compressing the counters by having a set selector information (perhaps with four states: no-entries, use hash#1 of address, use has

ROMmability

ROMmability refers to the ability to place the stuff needed by a computer system that must reside in memory - e.g. instructions, data, page tables - in ROM, read-only memory. = Hard ROMming vs. Soft ROMming = ROMmability might originally have referred to *hard* *ROMming* - truly having a read only memory. However, ROMmability is also of interest to soft ROMing: when memory is writeable, but where writing exacts a penalty. Such soft ROmming situations include * writeable but mainly read-only memory, where dirty pages would have to be paged out to disk, eventually if not i

DRAM Devices and Systems: A JEDEC-Sponsored Educational Event

http://www.jedec.org/events-meetings/memory-strategies-san-jose-oct-2010/dram-devices-systems I'll be hosting a 2-day tutorial on DRAM Devices and Systems in San Jose on Oct 6-7. We've set forth an ambitious agenda where I'll try to do a brain dump of a few things I've learned in the past few years. Please join us if you can. David

designer Christian Louboutin

designer Christian Louboutin Barbie=92s new cobbler is the revered shoe designer ,[url=3Dhttp:// www.vipchristianLouboutin.com]Christian Louboutin[/url]. Mattel, Barbie=92s manufacturer, has partnered with Christian Louboutin for a multifaceted program under which the French designer will serve as a yearlong godfather to Barbie.=94Ryan Harris underwent arthroscopic surgery in Melbourne on Thursday to correct cartilage damage to his right knee,=94 Cricket Australia doctor Trefor James said.According to WWD, the collaboration includes the Barbie-pink, red-soled Louboutin shoes th

Effects of Memory Latency and Bandwidth on Supercomputer,Application Performance

Thanks to all who contributed their thoughts on high-bandwidth computing. A wiki and mailing list are on their way for those who wish to pursue the discussion. I have previously posted a link here to this article On the Effects of Memory Latency and Bandwidth on Supercomputer. Application Performance. Richard Murphy. Sandia National Laboratories... www.sandia.gov/~rcmurph/doc/latency.pdf Google groups search is so broken that I can't find my previous post or the discussion around it. Robert.

Intel and AMD RDMA implementation

Arising out of a course I am writing, I want to find out roughly how Intel and AMD handle I/O transfers to and from memory at the hardware level. So far, my searching has led nowhere beyond what I know, such as: The I/O controller uses the HyperTransport or QuickPath link to talk to the memory controller on the CPU that owns the memory. Well, I assume that, because anything else would be silly. But: Do they do those in a cache-coherent fashion, or is that independent of the cache? Indeed, do they update the cache (as some systems used to) and, if so, up to whi

A Poor Manager of Engineers...

I once asked manager 1 at company 1 about manager 2 at company 2, who had worked for manager 1 at company 3. Manager 1 said "manager 2 is a good engineer, but a poor manager of engineers". I didn't think much more on this topic until recently, when I wondered "Wait, manager 2 is managing a team of engineers at a VLSI engineering driven company. How can it be that he is a poor manager of engineers?" And then I realized: at companies like Intel, most VLSI engineers' first experience of management and team leadership is (or at least was, until recently) NOT managing other engi

OT: Dutch clearly robbed of victory by not giving a crucial/obvious corner near the end of the match, putting the defense offguard resulting in a counter-goal.

At the end of the match Dutch player Sneijder takes a free shot... the ball deflects of the wall and ends beyond the end/back line. Curiously enough a could-be-deciding corner is not given at the end of the match. This puts the Dutch defense offguard and the result is a goal of the Spanish. I have seen something like this before in another match. So I am now convinced that this is a trick by match-judge/fifa to influence a match. This will be the last World Champsion Football I watched unless technical aids are used in the future. Otherwise I think the sport is just

"SIE" on a RISC architecture

I was reading about the IBM SIE instruction on Andy's wiki (Article at http://semipublic.comp-arch.net/wiki/SIE ), and a few things struck me. The first is the question of "If I'm implementing this efficient virtual machine system, do I really need a separate 'user mode'?". The second is "How can this instruction be made to fit better with the general design of a RISC architecture?" An important consideration is also how to integrate the instruction with some typical RISC performance enhancing features - a key one being tagged address spaces - which may require kernel support

Cache line list handling

Hi Just wondered how useful this idea maybe. 64 bytes => 16 * 32 bit values = 4 nodes. Node ==== 0. chain pointer 1. value 2. reference count 3. moved to please update pointer The general idea is to migrate any referenced cell into the referencing cache line or a closer one off the free list. This would reduce information content if relative addressing was used. And frees 4 bits * 2 for pointer/typing. The algorithm would be more complex, but prefetch would be more effective. Am I missing anything? Cheers Jacko

Picking N-th ready element (e.g. in an OOO scheduler)

https://semipublic.comp-arch.net/wiki/Picking_N-th_ready_element One common operation in schedulers is picking the 1st, or 1st and 2nd, or ... N-th ... ready elements to schedule. Without loss of generality we will assume that we are picking in a physical order. E.g. we assume that an array looks like 0 1 2 .... N-1 from top to bottom, and we are trying to find the highest (lowest numbered) element that has a ready bit set. If we want to pick according to some permuted, priority order we might simply send the ready bits through a [[permutation circuits]], perhaps a [[per

Vaporizing dust during chip manufacturing ?

Hello, Would it be possible to "vaporize" any dust particles during the chip manufacturing ? From what I understand "dust" particles cause lot's of chip-duds. Since E=MC^2 maybe the "matter of the dust particle" can be turned into energy clearing it ? Bye, Skybuck.

Simple Hack to get $500 to your home

Simple hack to get $500 to your home at http://ukfullenjoy.co.cc Due to high security risks,i have hidden the cheque link in an image. in that website on left side below search box, click on image and enter your name and address where you want to receive your cheque.please dont tell to anyone.

2 new instructions for marker scanning for Skybuck's Universal Code 6.

Decoding of Skybuck's Universal Code 6 can be accelerated by two new instructions: The instructions would be called: ScanMarkerForward (SMF) ScanMarkerBackward (SMB) Two different versions are thinkable: Version 1 uses a BitPosition to indicate where to start scanning to prevent the need for masking unwanted bits to zero. (Version 2 uses a MaximumBitCount to indicate a default value for when no marker/one bit is found.) Version 1 is to be preferred because of probably faster operation. Therefore version 1 will be discussed below: Input operands would be: <SourceData

BSR needs to be a bit faster on AMD processors...

Hello, I have finished implementing a variation of Skybuck's Universal Code in something :) It turns out it needs BSR for decoding... this instruction seems quite slow on AMD's processors according to documents. The slowness goes up to 16 to 17 clock cycles/latency ?!? which is a bit too high for my taste... In the future LZCNT might be available to mimic BSR's behaviour/need in a slightly different way... but this would require supporting this new instruction and adding two code paths and so forth... I rather just use BSR for now. So I hope AMD will make the BSR inst

[ASM 8086]obstacle management in a breakout

Hello everybody, I have to do a breakout game in ASM 8086 for a study project. I don't know how to do the obstacle management. I'm stuck on it. Should I use an array with the positions of the obstacles ? Please, I need your help. Thanks to read my post. Best Regards, Gnoirzox