f



Is this arch. workable? (DIY CPU)

G'day,

I have a bit of free time, and I'd like to try and make my own
Microcontroller (yes, a huge job, I know). I have decided to use an
existing CPU (PIC series) to emulate my CPU as a beginning, and then
progressivly add external components until I have just standard logic
chips and PLD's.

Howver, before I start, can anyone please review my initial brief
design document, and let me know your thoughts? I'd like to know if
I've overlooked anything that might make this design unworkable. This
is only a brief overview of the design - more detailed specs will be
written later.

Please be gentle - although I'm decent with microcontrollers, this is
the first time I've ever built one!

I realise the archecture isn't exactly elegant - but I'm attached to
it :-)

The Return Stack / Processing stack are stored in a single 8KByte SRAM
chip for the time being.

-----------------------


Altium Specifications - Revision .3


---------------------

Overview:

The Altium is an 8 bit Harvard Archevture Stack Machine. From the
programmers perspective, it has 3 main memory areas:

ROM: 8 bits wide, maximum size 64 kBytes. Stores the program. Can be
indirectly read via the LdROM Instruction.

Registers: The Altium has 40 bytewide registers, called R0 to R39.
These can be used with the LdReg and StReg instructions.

Processing Stack: The Processing Stack is a bytewide data structure
that forms the heart of the Altium. Most instructions get their
arguements directly from the Stack, and return their results on the
Stack.

Note that the Processing Stack is logically seperate from the Return
Stack (The Return Stack is invisible to the user). This arrangement
has several benefits. For instance, it allows functions to easily
return more then one result.

------------------------

Instruction Set:

The Altium has the following Instructions Set Archecture:


Math / Logical Instructions:

ADD	A,B -> (A+B)
SUB	A,B -> (A-B)
MUL	A,B -> (A*B Hi Byte):(A*B Lo Byte)
AND	A,B -> (A&B)
NOT	A -> !A
OR	A,B -> (A|B)
XOR	A,B -> (A XOR B)
ROL	A -> (A*2)
ROR	A -> (A/2)
INC	A -> (A+1)
DEC	A -> (A-1)

Stack Maniulation Instructions:

/n	Pushes an Integer Constant, n, on the Stack. 
DUP	Makes a copy of the TOS (Top of Stack)
DUP2	Makes a copy of the Top 2 Stack Levels
SWAP	Swaps Stack Levels 1 and 2
ROT	Rotates the Top 3 Stack Levels. EG S3:=S2, S2:=S1, S1:=S3
POP	Pop and Discard the TOS

Control Instructions:

Jmp xx		Jumps to location xx
jmpz xx		Pops the Top of Stack (TOS). If its Zero, then jumps to
location xx.
jmpnz xx	Pops the Top of Stack (TOS). If its Nonzero, then jumps to
location xx.
jmpc xx		If the Carry flag is Set, if so jumps to location xx
jmpnc xx	If the Carry flag is Clear, if so jumps to location xx
jmpe xx 	Pops the TOS, and compares it with stck level 2. If Equal,
jump to xx
jmpne xx 	Pops the TOS, and compares it with stck level 2. If Not
equal, jump to xx
Call xx		Saves the current address + 1 to the Return Stack, and jumps
to xx
Return		Pops the Return Stack, and jumps to that location

Memory Instructions:

LdReg	Pops the desired regster number from the Stack and Pushes the
contents of the Register
StReg	Pops the register number and Data from the stack, and stores it.
LdROM	Pops a 16 bit Address from the Stack, and pushes the contents of
ROM at that address.

Special Instructions:

Xmit	Pops the TOS, and sends it via serial port to Host PC for
debugging
Inp	Reads the Input Port, and Pushes the result
OutP	Pops the TOS, and writes it to the Output Port
----------------------

Example Altium Assembly Programs

---

To add 5 and 6, and store the result in Register 9:

/5	;Push 5
/6	;Push 6	
Add	;TOS contains result 
/9	; Push 9
StReg	; Result is stored into register 9

---

To Add the top 3 numbers on the Stack, and triple the result, and send
it to serial port

Add	;Add the top
Add	;3 stack levels
/3	;Push 3
Mul	;Multiply
Xmit	;Send result to serial port

---

To Calculate 5!, and send it to the serial port

/5 ; Push 5
Call Factorial ; Find the Factorial
Xmit	;Result is sent to serial port

Factorial:	;Pre: TOS contains n, where n! < 256. Post: TOS Contains n!

dup 		; Copy the TOS
jumpz GotZero	; if n = 0, result is one
Dup		; Make a Copy of n for the recursize call
Dec		; Decrement TOS
Call Factorial	; Find factorial of (n-1)
Mul		; TOS contains n * (n-1)!
pop		; get rid of the high byte
Return		; We're Done

GotZero:

/1 		; Push 1
Return		; Done

---

To Send a String Stored in ROM at Location 123:231 to the Serial Port.
Assume the string is terminated with a DollarSign.

EG "Hello, World! How are you today?$" With the leading H @ 123:231

/123 ; Push the hi Byte of the address of the String 
/231 ; Push the lo Byte of the address of the String 

Call SendString ; Send the String via serial port

<rest of program here>

SendString:	;Sends a dollarsign terminated string to the serial port
		;PRE: S1 = Lo Byte of ROM Pointer, S2 = Hi byte of ROM Pointer
		;POST: Stack = Stack - 2 Pointer Bytes

/1 		; Using Register 1 to store the LoByte
StReg 		; Store the Lo Byte of the pointer in Register 1
/0 		; Using Register 0 to store the HiByte
StReg		; Store the Hi Byte of the pointer in Register 0
		
GetChar:	;Get the next character

/0
LdReg		;Push the Hi byte of the Pointer
/1
LdReg		;Push the Lo byte of the Pointer

LdROM		;Read a byte from ROM
/$		;Push a dollarsign
jmpe Done	;If we got a dollarsign, jump to Done

xmit		;Else, send the character to serial port
		
		;now we must increment the pointer

/1
LdReg		;Push the Lo byte of the Pointer
inc		;Increase it by one
dup		;Make a copy to check for later
/1
StReg		;Save the updated result back in R1
		;TOS contains updated lo byte, since we DUP'd 2 lines earlier
jmpz Overflow	;If it's zero after increment, the lo byte overflowed. 
		;We must increment the hi byte if so

jmp GetChar	;Get the Next Char

Overflow:	;we come here if the lo byte overflowed. we must increment
the hi byte of pointer

/0
LdReg		;Load the Hi byte from R0
inc		;increase it by one
/0
StReg		;Save the updated hi byte
jmp GetChar	;Get another char

Done:		;Have got a Dollarsign here, so clean up and finish

Pop		;get rid of the last char we got, eg the dollarsign 
		;Remember jmpe only pops one of it's arguements, so the other must
be popped now

Return		;Return
0
6/24/2003 8:00:49 AM
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Looks like a forth chip with a bunch of superfluous registers.

Also:

In article <27bf520c.0306240000.25492993@posting.google.com>,
Al Borowski <a.borowski@student.qut.edu.au> wrote:
> Registers: The Altium has 40 bytewide registers, called R0 to R39.
> These can be used with the LdReg and StReg instructions.

40 is a really strange number, unless you're counting in octal or hex.

Your register load/store operations look kind of expensive.

Have you considered treating the stack as your register bank, so
instead of streg and ldreg you have an "nth-item" instruction that
copies the nth item from the stack to its top?

So instead of: /1 streg /2 streg .... /1 ldreg

You  have: ... /3 nth

This does require keeping track of stack depth, but in practice that's
not proven an overwhelming problem.

But it does sound like you should have a look at Forth to get an idea
of where other people have gone with this idea.

-- 
#!/usr/bin/perl
$/="%\n";chomp(@_=<>);print$_[rand$.]

Peter da Silva, just another Perl poseur.
0
peter
6/24/2003 12:32:55 PM
Hi,

peter@abbnm.com (Peter da Silva) wrote in message news:<bd9gdn$p95$3@jeeves.eng.abbnm.com>...
> Looks like a forth chip with a bunch of superfluous registers.

I've never used forth. My inspiration was RPL / PicoJava, which has
given me a warped idea of how a chip should look like :-)

> > Registers: The Altium has 40 bytewide registers, called R0 to R39.
> > These can be used with the LdReg and StReg instructions.
> 
> 40 is a really strange number, unless you're counting in octal or hex.

True. I just happen to have 40 bytes free in the PIC chip I'm using to
microcode the first version of the Altium. The final version (built
with logic IC's / PLD's) may have 256 bytes of memory.

> 
> Your register load/store operations look kind of expensive.

Do you mean that alot of them will be required in a typical program?
If so, I agree with you. Effiecency isn't a big issue, but I see your
point.

> 
> Have you considered treating the stack as your register bank, so
> instead of streg and ldreg you have an "nth-item" instruction that
> copies the nth item from the stack to its top?
> 
> So instead of: /1 streg /2 streg .... /1 ldreg
> 
> You  have: ... /3 nth

Do you mean it will copy everything from the nth item up to the TOS
into registers/memory, like a 'Save Stack Tip' operation?

If so, I can imagine it would need 2 parameters: The beginning
destination register, and the number of items to copy.

Very handy instruction, but I can see its going to be tricky to
implement in hardware. Perhaps make it a pseudoinstruction, that the
assembler translates into a loop of regular instructions?

> 
> This does require keeping track of stack depth, but in practice that's
> not proven an overwhelming problem.

My design already keeps track of the stack depth, so that's no biggie.

> 
> But it does sound like you should have a look at Forth to get an idea
> of where other people have gone with this idea.

Will do.


Thanks for the help - you've given me alot to think about. 

My aim is to build a basic CPU as simply as possible... I don't care
if it take 1 second per instruction, just as long as it works!

cheers,

Al
0
a
6/25/2003 12:47:58 AM
> Some implemntation suggestions:
> First thing to do is to write a simulator, and at minimum an assembler.
> You may even want to write/adapt a compiler.

I'm working on an assembler and simulator at the moment, but a
compiler is probably a little too much work. Maybe later...


> Doing this on an embedded low-end CPU is not something I'd wish 
> on anyone.

It's not easy, but I would like to get some hardware into the picture
at some stage :-)

I may just have the PIC doing simple timing things, to supervise the
mass of dumb logic. Eventually I hope it won't be required.

> 
> Instead of using CPLDs, consider a small FPGA. They are cheap (much 
> cheaper than CPLD for the same amount of logic) and contains many
> more flip-flops and (the newer ones) more than enough memory.
> Performance shouldn't be an issue (you will be able to get at least
> several-MHz clock, even without any optimizations).

I'll look into that. Thanks for the tip.

> 
> If you ever reach the design-verification stage (f you don't run out
> of motivation), you can compare the results of H/W and S/W simulations. 
> At this stage, you may want to write a "random program generator" program - 
> something which generates a random sequence of instructions, possibly with 
> some logic to prevent totally idiotic errors (e.g. reading from a non-existent 
> memory location or popping from an empty stack).

Interesting idea. I'll probably just be content with knowing simple
programs of mine run though.


----------------

Thanks for the reply to you and everyone else who responded. I just
wanted to make sure I hadn't left out any vital instructions!

cheers,

Al
0
a
6/26/2003 10:15:29 PM
a.borowski@student.qut.edu.au (Al Borowski) wrote in message news:<27bf520c.0306240000.25492993@posting.google.com>...
> G'day,
> 
> I have a bit of free time, and I'd like to try and make my own
> Microcontroller (yes, a huge job, I know). I have decided to use an
> existing CPU (PIC series) to emulate my CPU as a beginning, and then
> progressivly add external components until I have just standard logic
> chips and PLD's.

Curious choice, normally implementing a software simulation of
your CPU (and surrounding architecture) is both more common and
easier.  Simulating with VHDL or Verilog is also possible and
will allow you to transfer the design to a FPGA or ASIC later
with little more than a compile cycle on the right tools.

[snip]

> I realise the archecture isn't exactly elegant - but I'm attached to
> it :-)

We all love our own designs; until we invent a better one :-)

> The Return Stack / Processing stack are stored in a single 8KByte SRAM
> chip for the time being.
> 
> -----------------------
> 
> 
> Altium Specifications - Revision .3

If name it as *ium it may well sink :-)

[snip]

Seems a fairly normal stack based procesor, though,
with its limited memory capacity, implementation
as a harvard architecture seems inefficient, with
many FPGA chips you could embed the entire ROM on
the processor die (reducing pin costs, decreasing
memory latency and eliminating the need for a ROM.)
Implementing this memory as RAM and loading from
a ROM on processor reset would be more efficient.

The registers seem largely unnecessary.  I would only
implement two or four registers and use them for
addressing memory (such as load/store with increment,
or load/store at register with offset) this should
help in addressing lists or arrays, either by stepping
through the list or accessing at an index.

40 registers is an unusual number, 32 or 64 is more
common.  Are the remaining 14 used for specific
purposes? (ie. programme counter, stack pointer, etc.)

Also loading/storing relative to the stack pointer
would be useful (similar to you DUP opcode, just able
to access further up the stack.)

A seperate return stack is a good idea, though some
instructions for manupulating said stack would be
useful for writing an operating system, load/store
the stack pointer should be sufficient though push
and pop would be a useful addition.

You seem not to have mentioned interrupts in your
design notes, having some form of interrupt is
common for nearly every processor - no matter how
small.

Incidentially, if you choose such a stack
architecture you may be advised to lookup Chris
Bailey's PhD thesis on stack processor implementation
and optimisation (UTSA Stack Architecture (?), Bailey,
1996, University of Teeside, UK - I think he is
currently working at the University of York, UK.)

Also a look around open cores (http://opencores.org)
will give you a look at what other people have done,
as well as a possible forum for publishing your
finialised design.

Finally, what usage do you envisage for your
processor?  Deciding a usage (other than a general
purpose design) could lead to new instructions or
optimisations allowing it to really shine in a
particular field.

Good luck!

C 2003/6/28
0
blackmarlin
6/28/2003 2:24:21 PM
Did you check :  www.fpgacpu.org   ?

(check the FPGA-CPU List, GR CPU, XSOC)

There were a lot of discussions about CPUs in FPGAs. From very small to 
very strange ...

Now it is pretty quiet ...

cheers & have fun

0
emanuel
6/28/2003 6:17:28 PM
"Al Borowski" <a.borowski@student.qut.edu.au> wrote in message
news:27bf520c.0306261415.13b79d66@posting.google.com...
> > Some implemntation suggestions:
> > First thing to do is to write a simulator, and at minimum an assembler.
> > You may even want to write/adapt a compiler.
>
> I'm working on an assembler and simulator at the moment, but a
> compiler is probably a little too much work. Maybe later...
>
>
> > Doing this on an embedded low-end CPU is not something I'd wish
> > on anyone.
>
> It's not easy, but I would like to get some hardware into the picture
> at some stage :-)
>
> I may just have the PIC doing simple timing things, to supervise the
> mass of dumb logic. Eventually I hope it won't be required.
>
> >
> > Instead of using CPLDs, consider a small FPGA. They are cheap (much
> > cheaper than CPLD for the same amount of logic) and contains many
> > more flip-flops and (the newer ones) more than enough memory.
> > Performance shouldn't be an issue (you will be able to get at least
> > several-MHz clock, even without any optimizations).
>
> I'll look into that. Thanks for the tip.

You should be able to fit a small micro(programmable state machine)
 into one of the newer xilinx coolrunner2
cplds  XC2C256

see the xilinx picoblaze. there is a version
(downloadable for free - have to register.only for use in xilinx products)
that fits in a  XC2C256 .
http://www.xilinx.com/ipcenter/processor_central/picoblaze/

The newer actel flash fpga's look nice.
Also no need for data flash or eeprom to store the bitstream.

For a cheap board  digilentinc has quite a good one
(make sure to get spartan2e as that has webpack support)
http://www.digilentinc.com/Catalog/digilab_2e.html
I've got one and use it with their dio1 board.
http://www.digilentinc.com/Catalog/digilab__io1.html

also xilinx coolrunner2 design kit
has the digilentinc x2c board  for US$50.
http://www.digilentinc.com/XC2/index.html
the one in the xilinx kit doesn't have the connectors or breadboard.

>
> >
> > If you ever reach the design-verification stage (f you don't run out
> > of motivation), you can compare the results of H/W and S/W simulations.
> > At this stage, you may want to write a "random program generator"
program -
> > something which generates a random sequence of instructions, possibly
with
> > some logic to prevent totally idiotic errors (e.g. reading from a
non-existent
> > memory location or popping from an empty stack).
>
> Interesting idea. I'll probably just be content with knowing simple
> programs of mine run though.
>
>
> Thanks for the reply to you and everyone else who responded. I just
> wanted to make sure I hadn't left out any vital instructions!
>
> cheers,
>
> Al

Going to make this a project on opencores ?
www.opencores.org
www.opencores.org/projects (make sure to select all in drop down box)

There are a couple of almost pic and avr soft micros.

look in news:comp.arch.fpga

if your using vhdl
news:comp.lang.vhdl

or verilog
news:comp.lang.verilog

Alex


0
Alex
6/29/2003 9:04:11 AM
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Hello, I'm trying to estimate a VAR model of two equations. - the portmanteau test shows that my residuals are cross correlated - one of my equation exihibit an ARCH pattern I cannot use the AUTOREG procedure as I have a system of equations to estimate. I cannot use the VARMAX procedure because it is not possible to impose an ARCH structure for one equation only. I guess I should opt for the proc MODEL. I think I can program it. The problem here is how to check that my model is the right one ? Do you know how to generated the diagnotic checks given by the Pro c VARMAX with the proc Mo...

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-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Is anyone using GNU arch as a replacement for CVS? I've been looking into using it seriously over the last few months, and I would be grateful if anyone could tell me how to overcome a few hurdles. arch looks like a nice system. My main problem is that it forces a particular way of working upon the user, whereas CVS does what you want (despite its other shortcomings). I'd like to find a way of overcoming these problems to make it more usable. With CVS, everything I "cvs add" is in CVS, everything else is not. ar...

arch and mcc
What is the correct way of specifying the arch when launching mcc? I want to force the use of the 32 bit version on a linux machine. i've tried mcc -glnx86, mcc glnx86, mcc -arch=glnx86 but in all cases the 64 bits version (.../glnxa64/mcc) is launched. Is there a way to force, system wise, the use of the 32 bit version without having to specify -glnx86 with every command? ...

gnu arch?
I'm wondering if there is a way to make VC or others interface with GNU Arch in a meaningful way. I have noticed that with GNU Emacs out of cvs, it does display my branch name where it would also display any relevant CVS information. I would like to do things like commit, update etc. I'm sure there is a good way to do this, but I haven't seen it. I know that Tom Lord and Miles Bader appear to both use emacs && arch, so I'm sure there is a clever interface for it. Any insight would be appreciated. ../matt -- m. kolb <muk@msu.edu> <muk@bender.cl.msu.ed...

ARCH is FULL
I am using Oracle 9.2.0.1 on my IBM AIX 5.1L System. I have a DB instance "prod" running on it for TESTING purposes. I have set the DB to ARCHIVELOG Mode and the archive destination to "/archive". I "do not" use this db frequently but I am surprised that even after that my Archive destination become FULL (100%) without any transactions - wonder why....? Can anyone point out as to why the ARCH keeps on archiving the DB evenif there are NO TRANSACTIONS....? Is there any way by which ARCH or ORACLE notifies you or pings you that your archive destination is FULL.....What is the best way to take these archive files on TAPE and then delete them....I am sure there has to be some automatic process.... Any related information on this is appreciated.... hari_om@hotmail.com (Hari Om) wrote in message news:<d1d5ebe4.0310151343.6147ecb4@posting.google.com>... > I am using Oracle 9.2.0.1 on my IBM AIX 5.1L System. > > I have a DB instance "prod" running on it for TESTING purposes. I have > set the DB to ARCHIVELOG Mode and the archive destination to > "/archive". > > I "do not" use this db frequently but I am surprised that even after > that my Archive destination become FULL (100%) without any > transactions - wonder why....? > > Can anyone point out as to why the ARCH keeps on archiving the DB > evenif there are NO TRANSACTIONS....? > > Is...

Computer Arch.
Hi, i was wondering if anyone could give me some advice on a components of a computer im about to build. ive never done this before so am interested if anyone has pros/cons regarding the hardware i have selected. MoBo - ASUS P4P800 VM Case - P160 CPU - intel P4 3.2 GHz hard drive - hitachi 160 GB/7200/8MB/SATA-150 or hard drive - western digital caviar WD2500JB 250GB/7200/DMA-ATA 100 RAM - corsair 1024 MB PC3200 DDR400 1GB any suggestions on power supply? i was thinking 380 min? i would appreciate any advice anyone can offer. im pretty sure all this is compatible.. thank you in advance ...

X arch
I am looking for a document which can explain the the architecture of X. Some place where i can find the difference between X server and clients, the exact functions of a window manager and desktops, device drivers etc. And how everything fits together. Thank you in advance AB On Sat, 19 Jul 2003 04:00:31 -0500, Mithaz staggered into the Black Sun and said: > I am looking for a document which can explain the the architecture of > X. http://xfree86.org/ , somewhere in the "Documentation" directory? Maybe the X-Window User HOWTO at http://tlpd.org/ ? > So...

How To Arch Text?
How can I create text in an arch shape in either Quark or Photoshop? Thanks. Sarah >How can I create text in an arch shape in either Quark or Photoshop? That's a bit like askig "How can I open cans with a bandsaw?" The reasonable answer is: Don't. Use the right tool for the job. Both Quark (at least modern versions) and Photoshop *can* arch text, in much the same way that a bandsaw *can* open a can, but you're better off using Illustrator, and a can opener, for those jobs. -- Art, literature, shareware, polyamory, kink, and more: http://www.xeromag.com/franklin....

OT: Keyboard.arch
Aset keyboard It has been said that the most common letters were taken off the home row of the first typewriter keyboard to slow down the typist and prevent jamming. On a Dvorak keyboard almost sixty percent of average text is typed from the home keys. Transposing the letters 'etni' with 'dfjk' would put more than 55% of text on the home keys, up from only 26% on the qwerty layout. Thats more than twice the text typed without lifting a finger. The change is quite pleasent and easy to learn. I hope you will pass this on. To put e, t, n and i back where they belong, there i...

arch ne age
nice cepos ...

Re: ARCH models
Ceylan, > Regression model: y=b.x=e > AR model for e: e(t)=d1.e(t-1)+...+dp.e(t-p)+a(t) > So, when we write > proc autoreg data=one; > model y=x/ dw archtest; > run; > archtest is testing the ARCH for e square or a square? looking at the manual, it seems the test is for a(t) square but, in your case, it is the same for e(t) square since you didn't specify the NLAG option for the autoregressive part. HTH, Rogerio. ...

can you help me arch
for computer arch more visit www.glu007.blogspot.com ...

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