Does anyone know whether PCIe is cache-coherent?

"Gerald Mey" <gerald.mey@arcor.de> wrote in message 
news:477136cb$0$16668$9b4e6d93@newsspool3.arcor-online.net...
> Does anyone know whether PCIe is cache-coherent?

RTFM  http://www.pcisig.org 

Del Cecchi schrieb:

>> Does anyone know whether PCIe is cache-coherent?

> RTFM  http://www.pcisig.org

The specs are not free, idiot.

Gerald Mey wrote:
> Del Cecchi schrieb:
> 
>>> Does anyone know whether PCIe is cache-coherent?
> 
>> RTFM  http://www.pcisig.org
> 
> The specs are not free, idiot.


Well, then I guess you are out of luck, if you don't need to know 75 
euro worth.  But my best guess is no it is not coherent.

merry chistmas

Gerald Mey <gerald.mey@arcor.de> wrote:
> Does anyone know whether PCIe is cache-coherent?

Could you be a little more specific as to what you mean by
'cache-coherent'?

Thanks.

YANSWBVCG schrieb:

>> Does anyone know whether PCIe is cache-coherent?

> Could you be a little more specific as to what you
> mean by 'cache-coherent'?

It means that memory-locations shared between devices and processors
remain cohrerent without any software-intervention and that hardware
does all tasks (snooping, write-back, invalidation) to provide this.

"Gerald Mey" <gerald.mey@arcor.de> wrote in message 
news:4772e8b7$0$17537$9b4e6d93@newsspool4.arcor-online.net...
> YANSWBVCG schrieb:
>
>>> Does anyone know whether PCIe is cache-coherent?
>
>> Could you be a little more specific as to what you
>> mean by 'cache-coherent'?
>
> It means that memory-locations shared between devices and processors
> remain cohrerent without any software-intervention and that hardware
> does all tasks (snooping, write-back, invalidation) to provide this.

My guess is that, like Plain PCI, it isn't.  In fact it isn't even peer 
to peer as I recall.

a quick search on pci coherent came up with

http://interconnects.blogspot.com/2007/01/pci-express-gets-coherent.html

http://www.docs.hp.com/en/A3725-96022/ch07s04.html

and especially
http://www.eetimes.com/news/design/showArticle.jhtml?articleID=193006384

you are welcome 

Del Cecchi schrieb:

> My guess is that, like Plain PCI, it isn't.

Eeee, plain PCI is coherent.

> a quick search on pci coherent came up with
> http://interconnects.blogspot.com/2007/01/pci-express-gets-coherent.html
> http://www.docs.hp.com/en/A3725-96022/ch07s04.html
> and especially
> http://www.eetimes.com/news/design/showArticle.jhtml?articleID=193006384

Thanks.

Gerald Mey <gerald.mey@arcor.de> wrote:

> YANSWBVCG schrieb:
> 
> >> Does anyone know whether PCIe is cache-coherent?
> 
> > Could you be a little more specific as to what you
> > mean by 'cache-coherent'?
> 
> It means that memory-locations shared between devices and processors
> remain cohrerent without any software-intervention and that hardware
> does all tasks (snooping, write-back, invalidation) to provide this.

You are worried about DMA leaving stale data in CPU caches, but not
considering caches in devices?

Usually cache-coherency is taken to be between caches.

-- 
Mvh./Regards,    Niels J�rgen Kruse,    Vanl�se, Denmark

On Dec 27, 11:16 am, Gerald Mey <gerald....@arcor.de> wrote:
> Del Cecchi schrieb:
>
> > My guess is that, like Plain PCI, it isn't.
>
> Eeee, plain PCI is coherent.
>

Plain PCI _host_ bridges could (but not should) be coherent. And in
general-purpose computers they normally are.
So when the device reads (through bus-master DMA) some location in the
host memory for which an up to date copy currently lives in the host
processor's cache then the typical host bridge handles all machinery
behind the scene and the device is provided with correct data. The
same is true for device writes - if stale copy of the data resides in
host processor's cache it's invalidated automagically.

However it is impossible to build PCI device (as opposed to host) that
has a coherent cache of system memory. Device has no way to tell to
the host bridge that he "owns" a cache line nor is device notified
about changes made in system memory by the host or other devices or
about others being interested in particular location.

I'd guess that PCIe is the same but I never read the official
standard.

Gerald Mey <gerald.mey@arcor.de> wrote:
> YANSWBVCG schrieb:
> 
>>> Does anyone know whether PCIe is cache-coherent?
> 
>> Could you be a little more specific as to what you
>> mean by 'cache-coherent'?
> 
> It means that memory-locations shared between devices and processors
> remain cohrerent without any software-intervention and that hardware
> does all tasks (snooping, write-back, invalidation) to provide this.

Thanks. The words 'cache' and 'coherent' are not present in the index
of Mindshare's book _PCI Express System Architecture_, nor in the
table of contents, so far as I am able to determine. PCIe is supposed
to be upward compatible with PCI, so if PCI is cache-coherent, then
one would expect PCIe to be so as well. Cache coherency is explicitly
dealt with in the Minshare book on PCI System Architecture.

Niels J�rgen Kruse schrieb:

> You are worried about DMA leaving stale data in CPU caches,
> but not considering caches in devices?

Not worried; just interested in whether PCIe is cache-coherent.

> Usually cache-coherency is taken to be between caches.

Of course, but I'm asked for coherency of PCIe-DMA-reads/-writes.

already5chosen@yahoo.com schrieb:

> Plain PCI _host_ bridges could (but not should) be coherent.

I know that and I was thinking about usual PC-systems which all
support cache-coherency of PCI-DMA-reads/-writes. AGP on the other
side isn't cache coherent (... on PC-systems *g*).

> However it is impossible to build PCI device (as opposed to host)
> that has a coherent cache of system memory.

That wasn't the thing I was thinking about and I don't believe that
anyone read my question in that way.

> I'd guess that PCIe is the same but I never read the official
> standard.

Maybe it's implementation-dependent.