f



RISC and code quality

How much of performance benefit of RISC is lost 
due to lack of compiler optimization and/or less 
RISC-appropriate algorithm choices (i.e., relative 
to x86)?

While the simpler decoding of RISC instructions 
might allow a 30% wider fetch bandwidth and 
perhaps 2 fewer pipeline stages, if one 
compensates for the larger workload per 
instruction in x86, RISC might not offer any 
advantage in fetch bandwidth (possibly even 
with compensating for the extra move operations 
required by a two-operand ISA).  With already 
deep pipelines (and aggressive branch 
prediction), this seems to leave cache bandwidth 
and re-ordering resources as the areas in 
which a RISC ISA could provide an advantage.  
However, if register allocation, pipeline 
scheduling, memory alias analysis, and 
similar optimizations are less aggressive, then 
a RISC could lose much of its potential 
performance benefits.

Given that compilers targetting x86 have 
less ability to provide such optimizations 
(due to the lack of registers and the 
side-effects of some operations [e.g., 
condition codes being set by many 
operations]), it seems that less work 
might be done to develop such optimizations.  
Even using a single call interface (which 
is convenient for the compiler and debugger) 
could hurt performance disproportionately 
for a RISC.

Is is possible that Intel's pushing of IPF 
might help push compiler technology (to 
the benefit of RISC as well as EPIC 
processors)?

Paul A. Clayton
just a former McD's grill worker and technophile

0
memorymorass
6/24/2003 12:03:35 PM
comp.arch 7611 articles. 0 followers. carchreader (32) is leader. Post Follow

0 Replies
929 Views

Similar Articles

[PageSpeed] 14

Reply: