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Why Did No Core Machines Have Cache ???

When I say "cache", I'm referring to memory that
implements an address-match range greater than
its physical implementation, and I'm referring
to an address-match capability at the word or
block level, not page-level.  That excludes the
CDC 6600 memory hierarchy of LCS/ECS and paging
hardware like that on the SDS 940.

So why didn't anybody implement cache back in
the days of core memory?  There were machines
such as the pdp-11/70 which implemented
semiconductor cache against a larger core memory
(during that window when core still held the
advantage of size).  But I don't remember any
machines which implemented a core cache against
a core main memory.  Why not?
0
Mark
6/25/2006 5:53:58 AM
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Mark Thorson wrote:

(snip)

> So why didn't anybody implement cache back in
> the days of core memory?  There were machines
> such as the pdp-11/70 which implemented
> semiconductor cache against a larger core memory
> (during that window when core still held the
> advantage of size).  But I don't remember any
> machines which implemented a core cache against
> a core main memory.  Why not?

As far as I know, the first machine with cache was the 360/85.
It was at that time that the idea of locality and potential
advantage of cache was discovered.  I believe it was core, but
I would have to look it up to be sure.  IBM did have some fast
cores for small memories so it is possible.  Core speed depends
on core size, and faster, smaller cores are harder to work with.

As I understand it, the first use of semiconductor memory for a 
processor, maybe excluding registers, was the protection keys
for the 360/91.

The result was that the 360/85 performance was close to that of
the 360/91, which didn't have cache, but had 16 way interleaved
750ns core for a 60ns cycle processor.

-- glen

0
glen
6/25/2006 6:12:14 AM
glen herrmannsfeldt <gah@ugcs.caltech.edu> writes:
> As far as I know, the first machine with cache was the 360/85.
> It was at that time that the idea of locality and potential
> advantage of cache was discovered.  I believe it was core, but
> I would have to look it up to be sure.  IBM did have some fast
> cores for small memories so it is possible.  Core speed depends
> on core size, and faster, smaller cores are harder to work with.
>
> As I understand it, the first use of semiconductor memory for a
> processor, maybe excluding registers, was the protection keys
> for the 360/91.
>
> The result was that the 360/85 performance was close to that of
> the 360/91, which didn't have cache, but had 16 way interleaved
> 750ns core for a 60ns cycle processor.
>
> -- glen 	

a little search engine use
http://www.cs.clemson.edu/~mark/admired_designs.html

and some more

Model   Announced               First Shipped   Withdrawn
85      January 30, 1968        December 1969   June 24, 1971
   	
Structural aspects of the System/360 Model 85, Part I: General organization
http://domino.research.ibm.com/tchjr/journalindex.nsf/495f80c9d0f539778525681e00724804/a846ccbbdfe8f77a85256bfa00685a32?OpenDocument

abstract:
 	
A basic design objective for the Model 85 was to add a computer to the
SYSTEM/360 line that offers high performance over a wide range of job
types. Simulation studies indicate that the Model 85 will provide an
average three- to five-fold increase in internal performance with main
storage capacities of up to four million bytes. This part of the paper
discusses the major elements of the Model 85 within the architectural
context of SYSTEM/360, including the addition of a high-speed buffer,
called a cache. Also summarized are the simulation studies that led to
use of the cache, selection of its parameters, and verification of
internal performance of the system.

.... snip ...

http://www.research.ibm.com/journal/sj/071/ibmsj0701B.pdf
0
Anne
6/25/2006 3:07:46 PM
"Anne & Lynn Wheeler" <lynn@garlic.com> wrote in message 
news:m31wtd2rzx.fsf@lhwlinux.garlic.com...
> glen herrmannsfeldt <gah@ugcs.caltech.edu> writes:
>> As far as I know, the first machine with cache was the 360/85.
>> It was at that time that the idea of locality and potential
>> advantage of cache was discovered.  I believe it was core, but
>> I would have to look it up to be sure.  IBM did have some fast
>> cores for small memories so it is possible.  Core speed depends
>> on core size, and faster, smaller cores are harder to work with.
>>
>> As I understand it, the first use of semiconductor memory for a
>> processor, maybe excluding registers, was the protection keys
>> for the 360/91.
>>
>> The result was that the 360/85 performance was close to that of
>> the 360/91, which didn't have cache, but had 16 way interleaved
>> 750ns core for a 60ns cycle processor.
>>
>> -- glen
>
> a little search engine use
> http://www.cs.clemson.edu/~mark/admired_designs.html
>
> and some more
>
> Model   Announced               First Shipped   Withdrawn
> 85      January 30, 1968        December 1969   June 24, 1971
>
> Structural aspects of the System/360 Model 85, Part I: General 
> organization
> http://domino.research.ibm.com/tchjr/journalindex.nsf/495f80c9d0f539778525681e00724804/a846ccbbdfe8f77a85256bfa00685a32?OpenDocument
>
> abstract:
>
> A basic design objective for the Model 85 was to add a computer to the
> SYSTEM/360 line that offers high performance over a wide range of job
> types. Simulation studies indicate that the Model 85 will provide an
> average three- to five-fold increase in internal performance with main
> storage capacities of up to four million bytes. This part of the paper
> discusses the major elements of the Model 85 within the architectural
> context of SYSTEM/360, including the addition of a high-speed buffer,
> called a cache. Also summarized are the simulation studies that led to
> use of the cache, selection of its parameters, and verification of
> internal performance of the system.
>
> ... snip ...
>
> http://www.research.ibm.com/journal/sj/071/ibmsj0701B.pdf

I believe this is the machine that led IBM to discover the importance of 
understanding metastability.  We had two of them in Rochester.  They led 
me to develop a habit of saving every 5 minutes when editing using our 
home grown MTMT system.  The rumor was that we got them after a large 
aerospace customer became  very very dissatisfied.

My take is that there wasn't enough speed advantage between fast and slow 
core to make a difference, particularily given the density of circuitry 
available.

del 


0
Del
6/25/2006 9:44:25 PM
On Sat, 24 Jun 2006 22:53:58 -0700, Mark Thorson <nospam@sonic.net>
wrote, in part:

>When I say "cache", I'm referring to memory that
>implements an address-match range greater than
>its physical implementation, and I'm referring
>to an address-match capability at the word or
>block level, not page-level.  That excludes the
>CDC 6600 memory hierarchy of LCS/ECS and paging
>hardware like that on the SDS 940.

That type of cache, as noted in another reply, was used by IBM on the
IBM 360/85, a core machine. Later, it was also used on the IBM 360/195,
a large machine which took the existing 360/91 design, implemented in
ASLT, and converted it to monolithic, and added cache as well. This,
too, was a core machine.

John Savard
http://www.quadibloc.com/index.html
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0
jsavard
6/26/2006 3:35:04 AM
On 26/6/06 04:35, in article 449f557b.2047936@news.usenetzone.com, "John
Savard" <jsavard@excxn.aNOSPAMb.cdn.invalid> wrote:

> On Sat, 24 Jun 2006 22:53:58 -0700, Mark Thorson <nospam@sonic.net>
> wrote, in part:
> 
>> When I say "cache", I'm referring to memory that
>> implements an address-match range greater than
>> its physical implementation, and I'm referring
>> to an address-match capability at the word or
>> block level, not page-level.  That excludes the
>> CDC 6600 memory hierarchy of LCS/ECS and paging
>> hardware like that on the SDS 940.
> 
> That type of cache, as noted in another reply, was used by IBM on the
> IBM 360/85, a core machine. Later, it was also used on the IBM 360/195,
> a large machine which took the existing 360/91 design, implemented in
> ASLT, and converted it to monolithic, and added cache as well. This,
> too, was a core machine.

The Atlas 2 "slave store", a 32-word I-cache aimed at offsetting the
longer access time of the Atlas 2 core (as against the original Atlas),
was described in a brochure of 1963. See:

  <http://www.chilton-computing.org.uk/acl/technology/atlas/p018.htm>

The slave store was not a faster core store, though;
if I recall correctly, it was made of tunnel diodes.
-- 
Bill Findlay
<surname><forename> chez blueyonder.co.uk


0
see
6/26/2006 2:37:56 PM
"(see below)" <yaldnif.w@blueyonder.co.uk> writes:

> The slave store was not a faster core store, though;
> if I recall correctly, it was made of tunnel diodes.

That's what's claimed in H&P Computer Architecture - A Quantitative
Approach.


Kai
-- 
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
0
Kai
6/26/2006 5:24:52 PM
I recall that Univac had a "thin film memory" computer at one point.
Was that a cache?  Or just a smaller memory that was used in addition
to main memory?

I agree with another responder that the reason for no core caches
was that core memory speed depends on core size, and once you 
develop the ability to string very small cores you might as well
make a large memory out of them.
-- 

jhhaynes at earthlink dot net

0
haynes
6/26/2006 7:10:25 PM
Jim Haynes wrote:
> 
> I agree with another responder that the reason for no core
> caches was that core memory speed depends on core size,
> and once you develop the ability to string very small cores
> you might as well make a large memory out of them.

But you could make shorter rows and columns
in a small cache memory, which would be much
faster because you could drive them harder.
In some core machines, heat was the performance
limiter on the memory.
0
Mark
6/27/2006 1:10:44 AM
Jim Haynes wrote:
> I recall that Univac had a "thin film memory" computer at one point.
> Was that a cache?  Or just a smaller memory that was used in addition
> to main memory?
>
> I agree with another responder that the reason for no core caches
> was that core memory speed depends on core size, and once you
> develop the ability to string very small cores you might as well
> make a large memory out of them.
> --
>
> jhhaynes at earthlink dot net

The Univac 1110 used to come with both plated wire
(AKA "thin film"?) memory and core memory.
The former was faster than the latter, and there was
less of it.
The plated wire memory was not a cache for the core
memory as one thinks of such things today because it
was up to the operating system rather than hardware
to try to place and keep higher use "stuff" in the
region of the address space backed up by the plated
wire memory.
This was before my time so I don't know how well it
worked, but I vaguely seem to recall old-timers
complaining that it was a pain in the behind.

0
l_cole
6/27/2006 2:44:40 AM
On Mon, 26 Jun 2006 19:10:25 GMT, haynes@alumni.uark.edu (Jim Haynes)
wrote, in part:

>I recall that Univac had a "thin film memory" computer at one point.
>Was that a cache?  Or just a smaller memory that was used in addition
>to main memory?

The Univac 1107 used a small thin film memory for its register bank.

They also made some computers for the military with thin film memory for
their entire memory.

But cache in the modern sense, as the OP asked about, was invented by
IBM for the IBM System/360 model 85.

John Savard
http://www.quadibloc.com/index.html
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jsavard
6/27/2006 2:53:49 AM
On Sun, 25 Jun 2006 16:44:25 -0500, "Del Cecchi"
<delcecchiofthenorth@gmail.com> wrote, in part:

>My take is that there wasn't enough speed advantage between fast and slow 
>core to make a difference, particularily given the density of circuitry 
>available.

Core memories varied between a 10 microsecond cycle time to ones below 2
microseconds. The Packard-Bell 440 computer, an early microprogrammable
computer from around 1964 built from discrete transistors, used cores
with a cycle time of 5 microseconds, and biaxial cores with a cycle time
of 1 microsecond for microcode.

Instead, the factors mitigating against someone inventing cache sooner
were:

- Earlier machines tended to have small memories, from 4K to 32K words,
which would have been about the same size as a cache;

- Arithmetic-logic operations took times comparable with memory
accesses; and

- Newer computers had new instruction sets.

That last point explains why cache wasn't invented for the Control Data
6600. It was a new architecture; having a 32 K address space kept the
size of the instructions down, and so programs could use explicit block
move instructions from the larger core memory when needed, for better
optimization with less hardware.

On the other hand, the System/360 used base registers to achieve an
address space of 16 Megabytes. It was a compatible line of computers
introduced in 1964, so when problems arose in obtaining sufficient
supplies of a new, faster memory, a way of allowing a small fast memory
plus a large slow one to almost match a large fast memory that was
*invisible to the programmer* was needed.

Necessity is the mother of invention - and IBM had the right combination
of necessities to justify taking the time to investigate something like
cache as it prepared to make the Model 85 available.

John Savard
http://www.quadibloc.com/index.html
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seewebsite
6/27/2006 2:52:14 PM
In article <44a143ff.8582202@news.usenetzone.com>, 
seewebsite@excxn.aNOSPAMb.cdn.invalid says...
>
>On Sun, 25 Jun 2006 16:44:25 -0500, "Del Cecchi"
><delcecchiofthenorth@gmail.com> wrote, in part:
>
>>My take is that there wasn't enough speed advantage between fast and 
slow 
>>core to make a difference, particularily given the density of circuitry 
>>available.
>
>Core memories varied between a 10 microsecond cycle time to ones below 2
>microseconds. The Packard-Bell 440 computer, an early microprogrammable
>computer from around 1964 built from discrete transistors, used cores
>with a cycle time of 5 microseconds, and biaxial cores with a cycle time
>of 1 microsecond for microcode.
>
>Instead, the factors mitigating against someone inventing cache sooner
>were:
>
>- Earlier machines tended to have small memories, from 4K to 32K words,
>which would have been about the same size as a cache;
>
>- Arithmetic-logic operations took times comparable with memory
>accesses; and
>
>- Newer computers had new instruction sets.
>
>That last point explains why cache wasn't invented for the Control Data
>6600. It was a new architecture; having a 32 K address space kept the
>size of the instructions down, and so programs could use explicit block
>move instructions from the larger core memory when needed, for better
>optimization with less hardware.
>
I don't quite agree with your analysis (besides, a CDC 6600 could address 
128K (60 bit) words of memory, or almost a megabyte, not particularly 
small for the time).  The memory cycle time was 1 us, but the machine 
cycle time was 100ns.  A memory access could be started every cycle.  
Between the (for the time) large register set (8 60 bit "X", 8 18 bit "B", 
and 8 18 bit "A" registers), and the 32 way memory interleave, programs 
could be written that were fairly efficient.  The (2?, 3?) instruction 
word prefetch (and up to 4 instructions per word) and the loop "stack" (8 
words?) kept the instruction decoder fed.

It didn't need a cache because the memory system and the architecture were 
designed together.  I think it probably would have benefited from a cache, 
however.

			- Tim

0
tmm
6/27/2006 4:20:27 PM
On Tue, 27 Jun 2006 16:20:27 +0000 (UTC),
tmm@spamfilter.asns.tr.unisys.com (Tim McCaffrey) wrote, in part:

>I don't quite agree with your analysis (besides, a CDC 6600 could address 
>128K (60 bit) words of memory, or almost a megabyte, not particularly 
>small for the time).

You're quite right, that was a mistake on my part.

John Savard
http://www.quadibloc.com/index.html
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seewebsite
6/28/2006 3:22:02 AM
Mark Thorson wrote:
(snip)

> But you could make shorter rows and columns
> in a small cache memory, which would be much
> faster because you could drive them harder.
> In some core machines, heat was the performance
> limiter on the memory.

Some early IBM machines had the cores in oil for cooling.

I believe the 360/91 had 750ns core for main memory,
usually 2MB, but no cache.  The 360/85 came out later,
slower processor but with cache memory.  It does seem
that it was semiconductor memory.

The 360/91 protection keys are in semiconductor memory
in 16 bit chips, the first semiconductor memory used for
a memory subsystem.  (Registers don't count.)

-- glen

0
glen
7/14/2006 2:42:45 AM
Reply: