Flatten a list of cells
I want to flatten a list of some 2000 cells in a Vrtuoso library. I want to flatten pcells and symbolic vias too. The list is in an ascii file. How would I do this?
|
3/8/2010 9:17:39 PM
|
0
|
John Greene <u...@compgroups.net/>
|
|
|
Analog Layout
Hi
Can anybody tell me what is CIRANOVA . If I do my layout in
CIRANOVA , can i import it to virtuso layout editor.
Cheers
Sabyasachi
|
3/1/2010 9:28:23 PM
|
0
|
Sabyasachi <sabyasachi.iit...@gmail.com>
|
pcell Generation
Hi ,
Can anyone help me regarding pcell generation. My problem is
I want to make two matched capacitors
common centroid layout. I am using CPP (poly capcitance) as invidual
unit. I am using National Semiconductors 0.18um technolohy(cmos9). I
am able to generate pcell but cannot pass the parameter. How to pass
the parameters in pcell generation. Any tutorial for that.
cheers
Sabyasachi
|
2/28/2010 2:16:28 PM
|
1
|
Sabyasachi <sabyasachi.iit...@gmail.com>
|
Stretch, moving slow in Cadence 6
Hello all,
I am using Cadence IC 6.10 with latest patches on a Dell Xeon 1900
server which has 4 GB of RAM and runs RHEL 4.x WS. The cadence install
is kept on a file server which is mounted by these servers. We
generally remote login into the server from computers on the same
network. The windows PC has 512MB GeForce800 card and I use Xmanager
or X-Win32 for starting a X session. The machine itself has 4GB of RAM
and 3Ghz processor. The resolution is set to 1920X1080. I also used
another machine with 1680X1050 resolution.
When I am doing layouts and if I click the edge of a big p
|
2/26/2010 2:22:02 PM
|
2
|
Vaibhav <vgar...@gmail.com>
|
How to simulate a netlist - no schematic available????
Hi guys.
I have to simulate a netlist corresponding to a circuit, but I don't
have the schematic of that. How I can correctly simulate the topology
(AC simulation)?
I have tried simulating the netlist by ocean script after creating the
same directory structure as automatically created by cadence inside
the simulation directory [I created:
"/home/samiran/simulation/cell_name/spectre/schematic/netlist"
directories. Inside "netlist" folder, I placed "netlist",
"netlistFooter", "netlistHeader" files, and one more folder named -
"amap" and created all necessary files that should be re
|
2/23/2010 7:00:12 AM
|
6
|
Samiran <samiran....@gmail.com>
|
Unable to generate schematic from netlist!!!! Please help!
Hi All,
I am trying to generate schematic from a netlist using (File > Import
> CDL...) option. As input of CDL In GUI form, I entered:
CDL Netlist File: /home/sdam/netlist
Output Library: Samiran
Output View Name: schematic
Reference Library List: analogLib
The Input netlist is as follows:
---------------------------------------------------------------------------------------------------------------
// Library name: Samiran
// Cell name: TestMyCkt
// View name: schematic
COUTPUT (net9 0) capacitor c=1p
RM2 (0 net9) resistor r=1/gdM2
RM1 (net9 0) resistor r=1/gdM1
VINPUT
|
2/23/2010 6:41:50 AM
|
1
|
Samiran <samiran....@gmail.com>
|
Creating Contacts
In the Cadence VLE, we have the menu item "Create"->"Create Contact",
which can help us place an array of contacts with our own technology
file.
I am wondering that is there any existing SKILL function that I could
pass the parameters such as "row" and "column", to automatically place
an array of contacts without poping out the form???
I know there is a SKILL function called leHiCreateContact() opening
the "Create Contact" form where we can input the parameters. But I
want to automate the flow.
Thanks.
Ray
|
2/20/2010 1:43:57 AM
|
4
|
leileicats <leileic...@gmail.com>
|
Need help in understanding the simulation directory!!!!
Hi all,
Suppose I have a cell with name "samiran_test" for which a directory
has been created inside "Simulation" directory. There is one file in
the path: "Simulation/samiran_test/spectre/schematic/netlist/amap/
samiran_test.f.inst" whose content is as follows:
HEADER
"PSFversion" "1.00"
"C0v" "C0"
"C0n" "analogLib_cap_spectre"
"V1v" "V1"
"V1n" "analogLib_vsin_spectre"
"R3v" "R3"
"R3n" "analogLib_res_spectre"
"R11v" "R11"
"R11n" "analogLib_res_spectre"
"R5v" "R5"
"R5n" "analogLib_res_spectre"
"G5v" "G5"
"G5n" "analogLib_vccs_spectre"
"G2v" "G2"
"G2n" "analogLib_vccs_sp
|
2/18/2010 6:23:10 AM
|
1
|
Samiran <samiran....@gmail.com>
|
How to create a new funcyional button in encounter GUI window!
Hello,
I am looking for a example in tcl/tk or SKILL to create a new custom button in encounter GUI with new encounter menu.
Thanks!
Bobby
|
2/18/2010 5:14:46 AM
|
0
|
Bobby <u...@compgroups.net/>
|
Generate current and voltage ratings in schematics
Hello all,
Is it possible through skill to generate labels of current id
and voltages vds and vgs on corresponding nets for every transistor.
Here the values of id , vgs ,vds are obtained from simulation , from
Analog Design Environment window Results->Annotate->DC operating
points , would display all the important parameters for every
transistor, is it possible to get these values using skill and attach
them as labels on the nets.
Or else is there any other procedure to generate this labels of id ,
vds, vgs on the nets ,so that it is easy for layout engg to take
decision
|
2/18/2010 4:49:20 AM
|
12
|
sesi <sesikala...@gmail.com>
|
how to generate schematic from netlist?
Hi all,
How I can generate schematic from a given netlist in Virtuoso?
Cheers
Samiran
|
2/18/2010 4:44:58 AM
|
7
|
Samiran <samiran....@gmail.com>
|
Help with technology SKILL functions
I am trying to create a custom layer for annotation on a schematic
using SKILL in IC 6.1.3.500.16. Here is a sample of some of the SKILL
code. Note that this works pre-IC6.
cv = dbOpenCellViewByType("mylib" "mycell" myview") -> db:0xb....
tech_file_id = techGetTechFile(cv) -> db:0xb....
techGetLayerName(tech_file_id 10) -> nil
techCreateLayer(tech_file_id 10 "MY_layername") -> nil
The techCreateLayer call fails and I get this warning: "*WARNING*
techCreateLayer: Layer number 10 already exists".
If the warning is true, why did the call to techGetLayerName return
'nil'. Accord
|
2/17/2010 5:20:32 PM
|
4
|
Joel <joel_coo...@hotmail.com>
|
Stream-in with XStream (IC-OA 6.1.3): how to replace bit selector [x] with <x>
Hi,
I recently switched from IC-CDB 5.1.41 to IC-OA 6.1.3. As a matter of
fact, the stream-in/out tool PIPO has been replaced by XStream. The
transition went smoothly except for one thing:
For PIPO, the option "replaceBusBitChar" could be set to "true" in the
template file. This had the effect that signal names like mysignal[12]
were translated to mysignal<12> during stream-in and vice versa during
stream-out. It seems that such a functionality is not available for
XStream. The original option is not even mentioned in the PIPO->XStream
adoption guide and there is no further info
|
2/17/2010 2:43:46 PM
|
1
|
Thomas Popp <Thomas.P...@iaik.tugraz.at>
|
Net high light in schematic composer
When I am highlighting net by "9", it gets high light by dotted line. I want to highlight it by solid bold line.
How can I do that??
Thanks
|
2/17/2010 9:53:16 AM
|
1
|
Daksh <u...@compgroups.net/>
|
CAD Administrator/ Contract/ IN
Tom Gugger
Independent Recruiter
tgugger@bex.net
CAD Administrator/ Contract/ Indiana
We have a situation where a company is trying to pull together
drawings from
several systems to one system. Below is what he wrote to us. This
should be a
three month or longer assignment in Elkhart, IN. All work must be done
on-
Site. If you feel you can solve the problem below and are interested,
please forward
your resume to tgugger@bex.net.
=93We have a =93situation=94 here in Elkhart and I wondered if you may be i=
n
a position to help.
When we moved the Smith Specialty Group (S
|
2/16/2010 1:40:42 AM
|
0
|
TOM <tgug...@bex.net>
|
HELP: how to set Encounter to layout the shematic as it is?
I have a delay circuit built with 9 cascade inverters. The schematic
of this circuit was created in Cadence Virtuoso, then the netlist is
extracted and imported to SoC Encounter for layout. The problem is
that Encounter automatically eliminated 8 inverters from the circuit.
The question is: how to set Encounter to layout the circuit as it is?
Many thanks!
|
2/15/2010 8:39:44 PM
|
0
|
Dai Jiang <jiang...@gmail.com>
|
CAD/ SolidWorks/ Contract/ IN
Tom Gugger
Independent Recruiter
tgugger@bex.net
CAD/ Solid Works/ Contract/ Elkhart IN
We have an immediate start for an experienced person with solid
CAD experience using SolidWorks. Experience must be recent and
Not on an old version.
The site is in Elkhart Indiana, all work is done on sight, and the
rate
is $42hr. There are no expenses or benefits. The contract should last
until summer. Since there are no expenses, local and regional people
are preferred. Pay will be by 1099 or C to C.
We would like a Monday start date. Must be US Citizen or Greencard,
No
|
2/15/2010 7:26:08 PM
|
0
|
TOM <tgug...@bex.net>
|
to netlist a device for CDL but not for simulation
Hello,
I have 2 instances ( A and B ) of the same device in a schematic.
For simu I want to netlist only instance A
For LVS I want to netlist A and B
In other words for simu, I only want to netlist A and for LVS I want
to netlist A and B.
nlAction ignore is not a good idea because there is not difference
between simu and LVS
Thank you for your ideas .
Fred
|
2/11/2010 2:31:47 PM
|
3
|
=?ISO-8859-1?Q?Fr=E9d=E9ric_BATTIN?= <frederic.bat...@gmail.com>
|
Weird SKILL association table behaviour.
Hi,
I've got some weird results when creating a pcell.
When using rodCreatePath(), I used the ?size option as below:
-------------------------------------------------------------------------------------------------------------------------------------
?size ;B spacing + 1/2 width
max(techInfo[M1]->minSpa -techInfo[M1]->encOD + techInfo[NP]-
>spaOD +
techInfo[NP]->encOD - techInfo[M1]->encOD) +
(RING + 1/2.0)*M1Ring +
;C spacing + 1/2 width
RING*( max(techInfo[M1]->minSpa -techInfo[M1]->encOD +
techInfo[PP]->spaOD + techInfo[PP]->encOD -
|
2/11/2010 7:55:02 AM
|
2
|
I-F AB <cop0...@gmail.com>
|
extract or cut out a section in the layout
Does anyone have a way of either extracting or "cutting out" an area
of a layout? This will be used for
IR/EM analysis and running the whole chip would take a very very long
time.
Thanks
|
2/10/2010 6:32:36 PM
|
8
|
rick <ej...@pacbell.net>
|
OCEAN optimizeGoal documentation
Hi all!
I'm getting confused from reading the documentation to the OCEAN optimizeGoal
command.
1. in the description for b_percent: "Specifies whether the x_acceptable
field is a percentage of the target. When this is specified, x_acceptable
is ignored."
So I set this to say that
a) x_acceptable is meant to be a percentage value and
b) x_acceptable is to be ignored...
2. The example:
optimizeGoal( "bandwidth" 'bandwidth(v("/out") 3 "low") 'le 18M 15M )
I read this as "try and reduce the bandwidth below 18M. if this fails,
15M is acceptable".
Shoul
|
2/10/2010 5:44:29 PM
|
1
|
Joerg <jo...@sofort-mail.de>
|
CDB2OA translation error
Dear All
In IC 610, but when I use cdb2oa to translate, there are one
*ERROR*s. as follows:
********************************************************************************************************************
CDB2OA: cdb2oa -cdslibpath /home/mlpt2/temp/oa_convert/tsmcN90lo/ -lib
michael
cdb2oa.exe started. See cdb2oa.gui.log for details.
ERROR (CDBOA-107): You cannot run the translator in the same directory
as the
CDBA cds.lib file. Doing so would add OpenAccess library
definitions to the CDBA cds.lib file, which is not
permitted. Run the translator from a different directory.
cd
|
2/9/2010 8:36:48 PM
|
1
|
"btn_master...@googlegroups.com" <tanloongp...@gmail.com>
|
spectre error
Hi All,
I have Cadence installed in Sun Fire server (solaris 10). I use IC
5.10.41 IUS 82 and MMSIM 711.
When I run simulation in Virtuoso Analog Design Environnement this
message appear:
*Error* Simulator executable 'spectre' cannot be located from the path
$PATH
Use SetShellEnvVar () call to correct your path in CIW
Could you Help me please!
Regards,
Karim.
|
2/9/2010 1:45:40 PM
|
2
|
karim <abbeska...@gmail.com>
|
instance flip option missing in Schematic Editor.
Please let me know where can I find the "instance flip option missing
in Schematic Editor"?
--baps
|
2/9/2010 5:26:16 AM
|
1
|
baps <bapi....@gmail.com>
|
Results Browser Location Bar
I just want to ask if there is limitation on setting the Directory of
Location Bar on Results Browser?
I have a psf folder with the name: psf_npn1_pnp1
I could extract and plot the simulation result from this folder.
But when I set the environment variable of wavescan by the following
command:
envSetVal("wavescan.browser" "dataDirHome" 'string
"psf_npn1_pnp1")
It does not reflect on the Location Bar of Results Browser.
Does the wavescan.browser can't support the folder other than 'psf'?
I hope anyone could help me regarding this matter.
Thank you and God bless! (^_^
|
2/5/2010 8:32:33 AM
|
1
|
ecnedad <ecne...@gmail.com>
|
probe a huge number of devices - slow
Hi all,
I want to probe a huge number of instances into a schematic hierarchy.
There are about ~130 000 instances.
It tooks a lot of time, profiler shows me ~21 000 seconds spent in
geAddInstProbe();
The code for now is like:
//---------------------------------------------
wnd = geGetCellViewWindow(cv)
probeLpp = list("y0" "drawing")
foreach(inst instPathList
geAddInstProbe(wnd probeLpp inst)
)
//------------------------------------------
Is there any chance to spped up the code ?
Thank you,
Marcel
|
2/4/2010 9:58:08 PM
|
2
|
Marcel Preda <marcel.pr...@gmail.com>
|
Spectre Interactive Mode
Dear All,
I would like to know if there is a manual or reference for the
Interactive Skill Front End commands that are used in spectre
interactive mode. I searched in google and in Skill reference files
that come along with Cadence documentation, and can't find anything
useful till now.
The only thing I'm able to get is the list of possible commands:
sclGetParameter
sclListParameter
sclGetAttribute
sclSetAttribute
sclListAttribute
sclGetAnalysis
sclGetCircuit
sclGetInstance
sclGetModel
sclGetPrimitive
sclListAnalysis
sclList
|
2/4/2010 12:41:48 PM
|
2
|
Mohamed Tawfik <moh...@gmail.com>
|
Automatic Layout
Dear All,
I am Sabyasachi a student of Microelectronics & VLSI
Design in IIT Kharagpur. I am novice in SKILL Languge and in layout
automation. Could you please help me regarding layout automation in
cadence. Could you please give me some tutorial to learn this.
|
2/3/2010 8:28:35 PM
|
1
|
Sabyasachi <sabyasachi.iit...@gmail.com>
|
Limit multi-cut via array size
Hi!
I'm using
setNanoRouteMode -droutePostRouteSwapVia multiCut
routeDesign -viaOpt
in Encounter (9.1) to automatically convert single vias to multi-cut vias
after the initial routing.
The result is that I end up with via arrays of 50x50 vias since in parts
of the design lots of space is available, especially on higher layers.
Is there a way to limit size of the generated arrays to - say - 3x3 vias?
My vias are generated from a GENERATE DEFAULT rule. I guess removing the
generate rule and only explicitely defining small arrays would work, but
I would like to avoid that
|
2/2/2010 7:26:54 PM
|
1
|
Joerg <jo...@sofort-mail.de>
|
how to use CadenceSpace-Based Router
Dear All,
We are using IC613 Space-Based Router to do layout, A TSMC 65nm PDK
are used in our project,
I read Space-Based Router manual and I tried to follow the munual to
do the configuration ,
but it doesn't work. I don't know how to set the rules so that Space-
Based Router can work with TSMC 65nm PDK.
I did not get the points how to make Space-Based Router work with the
specified PDK.
How to configure or set the Space-Based Router so that it can work
with TSMC 65nm PDK correctly?
Regards,
Erick
|
2/1/2010 1:49:03 AM
|
15
|
Erick <erickrichard...@gmail.com>
|
Mirror the object, schematic
IC 5. How can I do mirror? What can i type in bindkey file?
|
1/31/2010 1:57:50 PM
|
1
|
StreAMnewal <streamw...@gmail.com>
|
Cadence ISSUE
Dear Sir,
I want to run ocean script from linux terminal.When I type 'ocean' I
get the error "command not found".I need to type 'tcsh'->'source
..cshrc1'->'ocean'.
Could you please tell me how to run ocean directly from the terminal
without using tcsh & then source .cshrc1.
Kindly help.
|
1/29/2010 2:47:40 PM
|
1
|
Supriyo Maji <supriy...@gmail.com>
|
cdb2oa error
Hi all,
I am using the conversion tool to convert the library from cdb to oa.
I always encounter some warning and this particular error while
performing.
It would be nice to know more about the error and why the tool from
assura is called while performing the conversion.
Thanks a lot
cheers
Dinac
*****************************************************
WARNING (CDBOA-639): There is more than one shape on the layer
prBoundary in
the cellview cells253cell/xn21d4/abstract. The
translator
creates an OpenAccess prBoundary object by usin
|
1/28/2010 4:12:21 PM
|
1
|
dinac <dines...@gmail.com>
|
Problem with Hierarchical Copy in IC6.1
Hi,
In IC6.1, I tried Copying a layout block hierarchically from one
library (say library A) to another newly created library (say library
B) using the "Copy View" form.
In the Copy view form,
I clicked the "Copy Hierarchical" option.
I clicked the "Update Instances" option.
I selected "Of Entire Library" against the "Update Instances" option.
(because the destination is a newly created library)
I wrote "layout" for the "Views To Copy" option.
With these options, After copying, the cells in the new library
( library B) is still refering to the old library (library A
|
1/28/2010 11:09:36 AM
|
0
|
RC MURALI <rcmur...@gmail.com>
|
select via array
I need select via arrays of different column/rows so I can change the
spacing and count due to a wide
metal rule violation. The search that works is for via by name which
wont allow me to select specific
configurations. Does anyone have a skill routine or something so I
can selective select the arrays?
Thanks
Rick
|
1/27/2010 10:39:39 PM
|
8
|
rick <ej...@pacbell.net>
|
machine/cpu recommendations for AMS sims
Hi,
I'm a bit out of touch with running large sims so could do with a bit
of help choosing an optimal configuration - used to use rack based
opterons but that was a while back.
I'm interested in some real world machine/cpu recommendations for
running AMS sims. I'm running veriloga and verilog rtl in AMS under
ADE - IC5141. ( at some point the real schematics will be swapped in )
OS
Using RHEL 4 - but I have a memory that RHEL5 was faster
32bit vs 64bit
TOOLS
IC5141_USR5 / Incisive_92 / MMSIM_62
again I think MMSIM7 was faster but we don't have time to swap so need
to stick w
|
1/27/2010 11:25:33 AM
|
2
|
gmc_99 <gerard.mccar...@gmail.com>
|
Stream out & Stream in: Virtuoso
Hi
I'm using Cadence virtuoso layout editor, I want to stream out and
stream In the GDS with preserving properties like "connectivity" and
"property" . Right now, i'm loosing those connectivity information
when i stream out GDS and stream In back. Could some help me in this
regard.
Thanks,
Kitty Movva.
|
1/24/2010 12:17:51 PM
|
4
|
Kitty Movva <kitty.mo...@gmail.com>
|
Cadence 6 Categories and Sub Categories
Hi,
I have a few questions about Cadence 6. I am a newbie so please bear
with me.
Ques 1 : When I create a new cell view using the Library Manager is
there a way I can specify the category ?
Ques 2: In the component browser, while inserting a new component, I
am unable to see subcategories is there a way to do that as well?
Thanks
Manu
|
1/23/2010 12:38:31 AM
|
3
|
Manu Rastogi <manurast...@gmail.com>
|
Threading with openResults() command
I am planning to have a threading of getting data from many psf Result
folder.
I am using Tcl/Tk and SKILL.
Now from Tcl/Tk Threading, I have distributed the Simulation Result
Extraction process into four local machine.
Example:
Local Machine:4
psf folders: /SimResult/test002 /SimResult/test003 /SimResult/test004
I just want to know if it is possible?
Because I'm thinking that since every time I used the openResults()
command, the results will be changed for the whole process. So the
value that has been extracted by getData() will be from only one psf
result folder.
Is t
|
1/22/2010 8:07:06 AM
|
3
|
ecnedad <ecne...@gmail.com>
|
Diva Latchup Check
I'm looking for a script that can scan a Layout and report any
possible latchup areas based on fet-to- sub/nwell contact space.
|
1/21/2010 12:13:24 PM
|
1
|
vtcad <roland.fonta...@gmail.com>
|
problem in oa2cdb conversion
Hi,
I was trying to convert a library in OA database to CDB through
command line, using the following command.
oa2cdb -lib TEST_LIB -cdslibpath /home/username/cds.lib -cdblibpath /
home/username/CDBLIB/ -tech /home/username/TECHLIB/tsmcN45
In the cds.lib file, the library TEST_LIB is defined.
The folder CDBLIB is newly & already created.
It gives the following errors after execution of the above command:
*WARNING* envGetVal: Could not find variable 'dbStatCacheOn'
in tool[.partition] 'cdba'.
*WARNING* envGetVal: Could not find variable 'dbInstNamingGlobalInc'
|
1/21/2010 4:57:35 AM
|
3
|
RC MURALI <rcmur...@gmail.com>
|
How to compare two schematics
Hi all,
How to compare two schematics using calibre or Assura.
Regards,
Sridhar.
|
1/20/2010 10:12:19 AM
|
1
|
BUS <sridhart...@gmail.com>
|
pwlf bus
Hi,
I want to use data from MATLAB as an input vector for my simulations.
In the past, I created a seperate pwlf source for each bit of the bus.
This worked good, for small small bus widths :).
Now my bus is becoming quite large (+64b).
What is the easiest way to import such data?
Pieter
|
1/19/2010 10:44:57 AM
|
5
|
pdw <dewit.pie...@gmail.com>
|
*Error* def : function is write protected and cannot be redefined
Hi,
I am getting the following message in icfb CIW, if I try to reload any
of my skill utilites.
*Error* def : function is write protected and cannot be redefined
How to get rid of this?
Thanks & Regards,
Murali RC
|
1/18/2010 10:11:26 AM
|
3
|
RC MURALI <rcmur...@gmail.com>
|
MonteCarlo Run in Ocean
Hello,
I am a new user of Ocean platform and I am using command interface
only (no GUI).
I want to estimate mean/sigma of a cell delay using monte carlo
analysis, but I am getting error. the error and scenario in mention
below:
Error: I am getting following run at the beginning of the monteRun().
ocean> monteRun()
Requesting Monte Carlo simulation...
*Error* parseString: argument #1 should be either a string or a symbol
(type template = "SS") - (-1e-08 0 1e-08)
ocean>
Netlist: I have a parameter "delL" in my netlist. Input signal node
name is "in" and output signal node na
|
1/17/2010 1:42:04 PM
|
0
|
Ashish Nigam <ashish.ni...@gmail.com>
|
Stimulus file
Hi all!
i would like to add the stimuli as file (defining it in the setup
window in the ADE)
and the input is a bus of sources.
I have something as:
_vb0 (b<0> 0) vsource wave=\[0 0 500.0n 0 500.3n 1.8 ] dc=0
type=pwl
_vb1 (b<1> 0) vsource wave=\[0 0 502.0n 0 502.3n 1.8 ] dc=0
type=pwl
Unfortunately it gives problem with the <>, i have tried with
underscore
(in that case it simulates but it does not recognize these nodes as
corresponding to b<1:0>) and with some backslash, but i am not able
to find a working solution.
Do you have some experience on it?
thanks in a
|
1/14/2010 4:32:13 PM
|
0
|
"ese!" <agnese.barga...@gmail.com>
|
view single layout net 5141
Hi all,
In days gone by i used a Skill function that could take a Diva
extracted view and create a new layout/extracted view with only the
metal,poly,via & contact of pre-selected net(s) remaining i.e all
other polygons were stripped away.
For example, you may wish to see a layout only with GND in it, so you
can review it's electromgration or weak points.
Is there something similar kicking about for Assura or PVS...or
perhaps
even 5141 has such a function hidden away? The "mark net" function is
close to what i want, but not quite.
Thanks
Stu
|
1/14/2010 3:30:44 PM
|
10
|
stuso <stuart.dun...@gigle.biz>
|
AMS simulation error
Hi all,
I am using IUS82, MMSIM 711, IC 6.1.3
I am trying to simulate a co-simulation of vhdl, verilog, and spectre
in config view.
The simulation stops with this errors (attached the part of the log
file below)
Thanks a lot for your help
Cheers
Dinac
********************************************************************************
.........
........
ncvlog: Memory Usage - 9.5M program + 8.7M data = 18.2M total
ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 90.4%
cpu)
Successfully compiled ('mixspi_vco' 'top_design' 'schematic').
Compilation successful
|
1/13/2010 9:30:55 AM
|
0
|
dinac <dines...@gmail.com>
|
Generate instance and net name labels from schematic
Hello all,
Is there any procedure in skill to generate attached labels of
instance names on instances and net names on the nets from the
schematic.
Given that the layout is LVS clean using calibre or assura so that we
get the connectivith information. And here how to get the net
information and instance names from the schematic rather than the
orginal
instance names(cv~>instances~>name) from the layout. Is it possible
through skill or else through Calibre or Assura itself.
|
1/13/2010 6:09:32 AM
|
2
|
sesi <sesikala...@gmail.com>
|
bBox routine to ignore "text" layer
All,
Here is the routine I came up with to ignore "text" layer. I use it
for layout. We want to get the dataextent but wanted the ability to
place text "outside" of the dataextent. Our tapeout data doesnt' have
the text in it anyways.
For example, we can place text for pad names, etc....
Does the routine look solid enough? Any comments to make it better
would be appreciated.
Thank you,
PolyPusher.
procedure(EFbBox()
let((cvbox EFbox EFLowestX EFLowestY EFHighestX EFHighestY EFFlag
EFPrevLowestX EFPrevLowestY EFPrevHighestX EFPrevHighestY Xvar
EFBoxVar
EFSkip EFdat
|
1/12/2010 4:09:23 PM
|
6
|
PolyPusher <eric.d.fitzsimm...@gmail.com>
|