(0.028 seconds) Articles (5428) |<First /272 Next>> Last >| Conditional statements in calculator 0 406 (8/31/2016 6:15:46 PM) Arun Issue in script to modify a routing blockage in Cadence SKILL 0 381 (8/25/2016 3:16:15 PM) AbdUllah Streaming in a GDS file in virtuoso 0 362 (7/14/2016 6:25:37 AM) sarik Cadence Virtuoso automatic routing wire width consideration 1 391 (7/13/2016 1:29:18 PM) mohammad . 0 379 (7/12/2016 4:51:01 AM) Nicholas Help needed for form creation. 1 484 (6/20/2016 8:02:10 AM) sandeep Netlist to schematic generation 0 376 (6/17/2016 4:30:32 AM) Muralidhar LNA power consumption of layout is less than schematic 2 400 (4/6/2016 12:33:04 PM) mohammad Problem with Skill Pcell loading and extracting 0 638 (3/4/2016 1:18:59 PM) Petyapop (1) Hi, I'm developing a skill pcell, but have a problem with loading it. I use two files one that has all my procedures and another that has the pcDefinePcell. I load the procedures file in the libInit.il file,... printing results for each value of dc sweep in spectre simulation 0 620 (3/4/2016 1:17:38 PM) S1234 (1) Hi i am running simualtion in dc sweep mode and its giving results. but i want result for each values of sweep which i am passing from file while running the simualtion. ex: dc_sweep dc param=lb start=0... Problem seeing the layout content of the instances 0 517 (3/4/2016 1:15:20 PM) Neo2012 (1) I'm no very professional in working with Cadence, but I've know the fundamentals. I am working with the 90nm technology but when I want to add a NMOS as top level a square can be seen with no label on it,( I've... Regarding the pcell creation 0 553 (2/18/2016 5:30:00 AM) keerthankumarkateel Cannot Netlist Verilog-A Model in Test Bench with Spectre/ADE/... 1 809 (1/27/2016 3:15:51 PM) Yuntao LVS for circuit using verilog-A model of transistor 0 691 (1/21/2016 1:01:01 AM) Doaa how to set history entries to save in ADEXL. 3 908 (1/3/2013 8:37:34 AM) yvk finding library 0.13u 0 849 (11/5/2015 2:51:22 PM) moein how to estimate the delay after floorplan , like i have a net 100 microns long. what will be the delay time , how to convert it into time delay (say this is 40nm tech)? 0 779 (10/30/2015 9:15:51 AM) n how to use setof to get the list what I want? 1 767 (10/12/2015 1:38:31 AM) Bo TSMC tech RF_NMOS layout problem in LVS (conflicting connections stamping layer sub) 0 687 (10/5/2015 2:33:43 PM) Sarsam SKILL Script needed to replace library and cell name of all instances in the cellview 1 1282 (9/2/2015 2:48:11 PM) del